IP Catalog > MIPI CSI-3 Receiver

MIPI CSI-3 Receiver IP

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Compare 5 IP from 3 vendors (1 - 5)
  • MIPI CSI-3 Verification IP
    • Supports Version 1.2 MIPI CSI-3 Specification
    • Supports transmission of Image frame
    • Supports transmission of Attribute packets
    • Supports Data transmission on multiple Virtual Channels
    Block Diagram -- MIPI CSI-3 Verification IP
  • High Performance Second Generation Extended MIPI CSI2 Receiver
    • Configurable 1, 2, 3 or 4 data lanes;
    • Configurable 1 or 2 clock lanes; 1,2,3,4 or 8 data lanes, when 8 data lanes option is ordered
    • 64 bit internal data bus
    • Optional 2 and 4 pixels output per clock
    Block Diagram -- High Performance Second Generation Extended MIPI CSI2 Receiver
  • Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock
    • 64 bit internal bus
    • 8 data lanes, with one or and 2 clock lanes in extended CSI2 mode
    • 1,2 or 4 24-bit pixels per clock
    • optional BER measurement
    Block Diagram -- Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock
  • MIPI M-PHY® 3.1 Analog Transceiver
    • The M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols.
    • The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII.
    • The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
    Block Diagram -- MIPI M-PHY® 3.1 Analog Transceiver
  • MIPI M-PHY® 4.1 Analog Transceiver
    • The M-PHY is of Type 1, which apply to UFS, LLI, and CSI-3 protocols. The Multi-gear M-PHY 4.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII.
    • The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
    Block Diagram -- MIPI M-PHY® 4.1 Analog Transceiver
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