LPDDR4 Super Combo Interface IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Compare 138 IP from 15 vendors (1 - 10)
  • DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
    • Supported DRAM type: DDR3L/DDR4/LPDDR4
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
    • Interface: SSTL135/POD12/LVSTL
    • Data path width scales in 32-bit increment
    Block Diagram -- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
  • DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
    • Supported DRAM type: DDR3L/DDR4/LPDDR4
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
    • Interface: SSTL135/POD12/LVSTL
    • Data path width scales in 32-bit increment
    Block Diagram -- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
  • DDR and LPDDR Combo PHY
    • Supports multiple combinations of DDR/LPDDR interfaces
    • Compliant with JEDEC DDR and LPDDR standards
    • Supports all auto calibrations
    • Industry leading area and power
  • LPDDR4X/4 & LPDDR5T/5X/5 Combo Controller
    • Support for all LPDDR4 and LPDDR5 devices
    • Bank management logic monitors status of each bank
  • LPDDR5X/5/4X/4 combo PHY at 7nm
    • Compliant with JEDEC JESD209-5B for LPDDR5X/5/4X/4 with PHY standards
    • Delivering up to 8533Mbps
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at 7nm
  • DDRx & LPDDRx DRAM Combo Memory Controller
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • I/O Library
    • Supports process nodes from 0.13um to 3nm
    • ESD protection: Robust ESD protection mechanisms ensuring device reliability and longevity
    • Temperature Range: Designed for wide operational temperature ranges, suitable for consumer, AI to automotive applications
    • Signal Integrity: Optimized for low noise and high signal integrity, ensuring reliable data transmission across all interfaces


    •  
  • Automotive IP Suite
    • Our silicon proven Automotive IP Suite offers versatile and robust IP solutions for high-speed data communication in automotive applications.
    • By supporting a wide range of industry standards, it provides automotive manufacturers with the flexibility and reliability needed to develop advanced, high-performance vehicle systems.
  • Simulation VIP for LPDDR4
    • Speed (Mt/s)
    • 2133MHz (4266MT/s)
    • Device Density
    • Supports a wide range of device densities from 4Gb to 32Gb
    Block Diagram -- Simulation VIP for LPDDR4
  • LPDDR4 Controller IIP
    • Supports LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4X and JESD209-4Y (Proposed) Specification.
    • Compliant with DFI version 4.0 or 5.0 Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
    Block Diagram -- LPDDR4 Controller IIP
×
Semiconductor IP