LPDDR Combo Controller - LPDDR4X/4 & LPDDR5T/5X/5
Overview
The Rambus LPDDR4 and LPDDR5 combo controller core is designed for use in applications requiring high memory throughput at low power including mobile, Internet of Things (IoT), automotive, laptop PCs, and edge networking devices.
Key Features
- Support for all LPDDR4 and LPDDR5 devices
- Bank management logic monitors status of each bank
- Queue-based user interface with reordering scheduler
- Look-ahead activate, precharge, and auto-precharge logic
- Parity protection for all stored control registers
- PHY interface based on DFI 5.1 standard
- Each controller instance supports a single channel
- Multiple rank support (typically 2 or 4)
- Supports WCK:CK ratio 4:1
- Supports x16 mode
- Burst length BL16 and BL32
- Data bus inversion (DBI) feature (read and/or write)
- Supports masked write (MWR)
- Mode register write (MRW) and mode register read (MRR) functions
- Background ZQ calibration mode and command-based ZQ calibration mode
- Supports LPDDR speeds up to 9.6 Gbps/pin
- Supports all defined LPDDR5 channel densities (up to and including 32Gb, including non-binary densities)
- LPDDR5 bank architecture BG mode and 16B mode
- LPDDR5 per-bank refresh and all-bank refresh
- LPDDR5 refresh management
- LPDDR5 device self-refresh mode
- LPDDR5 device power-down mode
- Automatic generation of initialization and refresh sequences
- Built-in activity monitor
- Optional multi-burst capability
- Full set of add-on cores available
- Can be delivered fully integrated and verified with target LPDDR PHY
- Customization and integration services available
Deliverables
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Technical Specifications
Foundry, Node
Any