I/O library TowerJazz 65nm IP

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Compare 580 IP from 28 vendors (1 - 10)
  • 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
  • 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
  • 0.9V/2.5V I/O Library in TSMC 55nm
    • This SoundWire Digital I/O Library in TSMC 55nm LP is a silicon-proven interface solution for high-performance au- dio applications.
    • Designed for 0.9V/2.5V operation, the Data, Clock, and Select I/Os, ensuring seamless integration with SoundWire-based systems.
    • Engineered for reliability, the I/O cells meet 2kV HBM, 500V CDM, and 8kV system-level ESD protection (150pF, 330 Ohm direct contact to housing), with 18kV air discharge capability, offering exceptional robustness against electrostatic and environmental stress.
    Block Diagram -- 0.9V/2.5V I/O Library in TSMC 55nm
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
    • A 3.3V wirebond I/O library with 8kV HBM ESD protection, a 1.2Gbps LVDS, GPIO, and I2C compliant ODIO in an ultra-small footprint.
    • This library ensures robust reliability in challenging environments, with capabilities including 8kV HBM, 500V CDM, and a robust 2kV IEC 61000-4-2 system stress capability.
    • Its compact footprint makes it ideal for applications where size is critical.
    Block Diagram -- High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
  • I/O Library in TSMC 130nm 5V Gen3 BCD
    • A TSMC 130nm Wirebond/Flipchip compatible I/O Library with 5V GPIO, 5V ODIO, 5V Analog I/O and 5V Power Supply I/O.
    • This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD protection scheme.
    Block Diagram -- I/O Library in TSMC 130nm 5V Gen3 BCD
  • Ultra-low leakage I/O Library in TSMC 22nm
    • A TSMC 22nm Wirebond / Flipchip I/O library with dynamically switchabe 1.8V/3.3V GPIO, 3.3V I2C ODIO, 3.3V Analog Cell and associated ESD.
    • This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA.
    • It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes.
    Block Diagram -- Ultra-low leakage I/O Library in TSMC 22nm
  • I/O Library
    • Supports process nodes from 0.13um to 3nm
    • ESD protection: Robust ESD protection mechanisms ensuring device reliability and longevity
    • Temperature Range: Designed for wide operational temperature ranges, suitable for consumer, AI to automotive applications
    • Signal Integrity: Optimized for low noise and high signal integrity, ensuring reliable data transmission across all interfaces

  • 55nm Specialized Analog I/O Library
    • Core Device: 2.5V Standard with 1.8V UD and 3.3V OD Devices
    • I/O Device: 1.8V
    • BEOL: 7 metals + RDL, 5 normal, 2 think (EA, EB), top LB
    • PAD: Flipchip, 60um pitch
  • A 65nm/55nm Wirebond IO Library with 1.2V to 3.3V GPIO and 5V ODIO
    • A 3.3V GPIO with two selectable inputs, slew rate control, and optional active tri-state.
    • A GPIO with an ultra-wide supply range and an optional glitch filter
    • A 5V tolerant Open drain IO with an optional glitch filter and programmable receiver thresholds
    • A 1.2V Open drain IO with two slew rate options.
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