GSM PHY IP

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Compare 3 IP from 2 vendors (1 - 3)
  • RapidIO Verification IP
    • Supports RapidIO specification 1.3, 2.0, 2.1, 2.2, 3.0, 3.1, 3.2, 4.0 and 4.1.
    • Supports Serial 1x/2x/4x/8x and 16x Physical lanes.
    • Supports 8b/10b and 64b/67b Encode and Decode functions.
    • Supports scrambler/Descrambler.
    Block Diagram -- RapidIO Verification IP
  • RapidIO Synthesizable Transactor
    • Supports RapidIO specification 1.3, 2.0, 2.1, 2.2, 3.0, 3.1, 3.2, 4.0 and 4.1.
    • Supports Serial 1x/2x/4x/8x and 16x Physical lanes.
    • Supports 25.78125Gbaud/s, 12.5Gbaud/s, 10.3125Gbaud/s, 6.25Gbaud/s, 5Gbaud/s,3.125 Gbaud/s, 2.5 Gbaud/s, 1.25 Gbaud/s.
    • 8b/10b Encode and Decode functions.
    Block Diagram -- RapidIO Synthesizable Transactor
  • CPRI
    • Designed to CPRI Specification v7.0
    • Suitable for use in both Radio Equipment, Controllers (RECs) and Radio Equipment (RE), including multi-hop systems
    • 7-Series, UltraScale and UltraScale Plus supported line rates in the Table 1 below
    • Automatic speed negotiation
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Semiconductor IP