CPRI
Overview
The LogiCORE™ CPRI IP core is a high-performance IP solution that implements the Common Public Radio Interface (CPRI). The IP core uses industry leading transceivers to implement the CPRI Physical Layer and provides a compact and customizable Data Link Layer implemented in the FPGA fabric. The CPRI core is ideal for connectivity between Radio Equipment Controllers (REC) or baseband/channel cards and one or more Radio Equipment units (RE). It provides an optimized implementation supporting radio I/Q data, radio unit management, and synchronization in a single efficient protocol.
Key Features
- Designed to CPRI Specification v7.0
- Suitable for use in both Radio Equipment, Controllers (RECs) and Radio Equipment (RE), including multi-hop systems
- 7-Series, UltraScale and UltraScale Plus supported line rates in the Table 1 below
- Automatic speed negotiation
- Configurable as master or slave, master instantiation can be switched to operate as slave via configuration port
- Supports both Ethernet and HDLC Control and Management channels
- Easy-to-use I/Q data interface together with optional modules for UMTS terrestrial radio access - frequency division duplexing (UTRA-FDD) and Evolved UMTS Terrestrial Radio Access (E-UTRA) data mappings
- Supports vendor-specific data transport including support for the passing of control AxC information in global system for mobile communications (GSM) systems
- Core includes the necessary clocking and transceiver logic to enable easy integration into your design
- Synthesizable example design and simple demonstration test bench provided
- Delay measurement capability meets CPRI Requirement 21 per CPRI Specification v7.0
- Reed-Solomon Forward Error Correction (RS-FEC) supported at 8,110.08 Mb/s, 10,137.6 Mb/s, 12,165.12 Mb/s and 24,330.24 Mb/s line rates