Flash memory IP

Compare 190 IP from 61 vendors (1 - 10)

Hyperbus Flash Memory Controller
- Compatible with spansion hyperbus based memory products.
- 0 Wait State Write Burst Operation for HyperBus memory on AXI interface of up to 256 words.
NAND Flash Memory Controller with DMA
- ONFI 4.0 support
- BCH EDAC with up to 60 bits correction capacity per 1024 bytes chunks of data
- Randomization of memory data
- Basic timeout based SEFI detection and reporting
xSPI Flash Memory Controller
- Compatible to most SPI protocols used by the NOR-Flash vendors including xSPI (JEDEC’s JESD251), and Xccela
- Single, Dual, Quad, Twin-Quad and Octal SPI lanes. Single and Dual Transfer Rate (STR and DTR)
- Programmable bit-length and number of SPI lanes used for command, address, latency (dummy cycle) and data. Programmable command encoding
- XIP - Allows AHB bus masters to read directly from the flash with zero software overhead.
Parallel FLASH Memory Controller
- Provides the physical interface between your FPGA/ASIC and the external FLASH
- Easy-to-use synchronous command interface
- JEDEC® standard Flash EEPROM pinouts and commands
- Fully configurable timing parameters to suit different manufacturers
External Flash Memory Interface IP
- AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
- Page-wise programming according to the flash memory requirements handled by the IP
- Memory single bit error detection and correction implemented in the IP-core.
- User configurable, industry standard NOR flash memories can be interfaced with the IP on SPI and Quad-SPI interfaces.
Flash Memory Endurance Extender / EEPROM Emulation
- Support EEPROM Emulation and Flash Memory in the Same Application
- Support Flash Memory and Flash Memory with Endurance Extension in the Same Application
- Available EEPROM Configuration Sizes (in Bytes): 128, 256, 512, 1024, and 2048
- Configurable Endurance Size from 1 to 128 Pages in Power of 2 Increments (i.e., 1, 2, 4, ..., 128)
The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- SuperFlash technology
- CMOS compatible
- Up to 500K cycle endurance
Flash Memory LDPC
- Quasi cyclic (QC) – Algebraic constructed – LDPC code
- Regular parity check matrix
- Codeword length: 16 K
- Code rate: 0.953
Flash Memory LDPC
- Irregular parity check matrix
- Layered decoding
- Minimum sum algorithm
- Soft decision decoding
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
- Master SPI Controller Targeting SPI Flash Memory Access
- SPI Flash Memory:
- Transmit/Receive FIFOs:
- Two Clock Domains:

Flash Memory IP