SPI NAND Flash Memory Model

Overview

SPI Nand Flash Memory Model provides an smart way to verify the SPI Nand Flash protocols.It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPI NAND Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI NAND Flash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Fully compatible with SPI Nand Flash standards.
Follows Nand Flash specification as defined in Micron specifications.
Supports all commands as per specifications.
Supports Master and Slave Mode
Supports automatic initialization after power up.
Supports software write protection with lock register
Supports hardware write protection to freeze BP bits
Supports Permanent block lock protection.
Supports single, dual and quad mode in command and data phase.
Supports following features,

Read page cache mode
Read unique ID
Read Parameter page

Supports Block erase commands.
Supports set feature and get feature commands
Supports ECC protection
Built in functional coverage analysis
Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPI Nand Flash bus.
Master contains rich set of commands.
Notifies the test bench of significant events such as transactions, warnings, and protocol violations.This can be written to separate log files.
SPI Nand Flash Memory Model comes with complete test suite to test every feature of SPI Nand Flash specification.

Benefits

Faster testbench development and more complete verification of SPI Nand Flash designs.
Easy to use command interface simplifies testbench control and configuration of slave and master.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SPI Nand Flash testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

Request Info