Doppler Channel IP
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9
IP
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9)
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Fixed Point Doppler Channel IP core
- The Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase offset.
- The IP was developed with the aim of allowing the performance evaluation of a low earth orbit (LEO) digital communication system.
- Unlike a software-based DSF generator, which might take several hours and even days for the stated purpose, a hardware-based DSF generator requires significantly less time.
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LTE Channel Estimation IP core
- Near-perfect-CSI performance
- Optimized for LTE Broadcast eMBMS
- One or more MCS level improvement
- Integrated timing, Doppler, SNR estimation
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Adaptive Interactive detection- Per-Survivor Processing
- MATLAB Simulation, Using FEC code
- Source codes (synthesizable VHDL/ Verilog/sys Gen Model) of PHY Components
- Design & Development of PHY Controller software
- PHY characterization and configuration
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DVBS2
- A flexible input stream adapter, suitable for operation with single and multiple input streams of various formats (packetized or continuous)
- A powerful FEC system based on low-density parity check (LDPC) codes concatenated with BCH codes, allowing quasi-error-free operation at approx. 0.7 dB to 1 dB from the Shannon limit, depending on the transmission mode
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Multi-LEO Satellite Link Emulator
- Multi-LEO Simulation
- Dynamic Channel Modelling
- Flexible Configuration
- Scalability
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ITS-G5/802.11p PHY/MAC
- SoC architecture
- Robust receiver including advanced Doppler signal processing
- Scalable solution
- On demand customization available
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Software Defined Radio with Spread spectrum and SOQPSK for Telemetry applications
- Spread Spectrum and SOQPK Radio
- Faster Signal Acquisition
- High Mobility & Doppler Support
- Long Range
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Mobile Phase Recovering Equalizer
- 17-tap complex-arithmetic LMS Channel Equalizer with adaptation bandwidth and leakage rate control as well as independent coefficient hold and reset controls
- VV4 Quasi-Coherent Demodulator for signal phase recovery and differential detection
- Integrated Symbol Slicer provides demodulated soft-decision outputs
- AGC output controls in proportional and up/dn format for constant-modulus and phase-locked processing