DDR3-2133/LPDDR2 Combo IP
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506
IP
from 41 vendors
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10)
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LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
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MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
- Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
- Support both MIPI DSI and CSI-2 protocols
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LPDDR5/4x/4 combo PHY on 14nm, 12nm
- JESD209-5A(LPDDR5), JESD209-4C(LPDDR4), JESD209-4-1(LPDDR4X) compliant
- Operating speed up to 6400Mbps in LPDDR5, 4266Mbps in LPDDR4X
- Multiple DFICLK : CK :WCK ratios
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MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
- Low power consumption, small area
- Supports both overdrive (0.85V) and normal (0.75V) power
- Support for various lane configurations
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MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 4nm
- Samsung Foundry 4nm low power enhanced (LN04LPE) CMOS device technology
- 1.2V±5%, 0.75/0.85V±5% power supply
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MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
- Samsung Foundry 5nm low power enhanced (LN05LPE) CMOS device technology
- 1.8V±5%, 1.2V±5%, 0.75/0.85V±5% power supply
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MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
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LPDDR5X/5/4X/4 combo PHY at 12nm
- Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
- Delivering up to 8533Mbps
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
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LPDDR5X/5/4X/4 combo PHY at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
- Channel equalization with FFE and DFE
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MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
