IP Catalog > DDR3-2133/LPDDR2 Combo

DDR3-2133/LPDDR2 Combo IP

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Compare 489 IP from 42 vendors (1 - 10)
  • eMMC/SD/SDIO Combo IP
    • The eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of applications
    • This IP integrates a host controller and PHY, enabling seamless communication with eMMC, SD, and SDIO devices
    • When connecting the SD/SDIO device, the IP supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed modes
    Block Diagram -- eMMC/SD/SDIO Combo IP
  • MIPI C/D Combo TX PHY and DSI controller
    • High Data Rates: Supports data transmission rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI CD-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    • Flexible IP Configuration


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    Block Diagram -- MIPI C/D Combo TX PHY and DSI controller
  • DDR and LPDDR Combo PHY
    • Supports multiple combinations of DDR/LPDDR interfaces
    • Compliant with JEDEC DDR and LPDDR standards
    • Supports all auto calibrations
    • Industry leading area and power
  • MIPI C/D Combo PHY RX - GlobalFoundries 22FDX
    • Supports up to one clock lane and four data lanes for DPHY1.2
    • Fully compliant with MIPI D-PHY v1.2 and C-PHY v1.0 spec
    • Available in GlobalFoundries 22FDX process
    • Three 3phase encoded data lanes for CPHY1.0
    Block Diagram -- MIPI C/D Combo PHY RX - GlobalFoundries 22FDX
  • MIPI C/D Combo PHY TX
    • Supports HS TX data rate up to 2.5Gbps (2.5Gsps) per lane (trio)
    • Fully compliant with MIPI D-PHY v1.2 and C-PHY v1.0 spec
    • Available in GlobalFoundries 22FDX process
    • Three 3phase encoded data lanes for CPHY1.0
    Block Diagram -- MIPI C/D Combo PHY TX
  • LPDDR4X/4 & LPDDR5T/5X/5 Combo Controller
    • Support for all LPDDR4 and LPDDR5 devices
    • Bank management logic monitors status of each bank
  • LPDDR5X/5/4X/4 combo PHY at 12nm
    • Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
    • Delivering up to 8533Mbps
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at 12nm
  • LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
    • Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • x16 and x32 channel support
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 8nm
    • Samsung Foundry 5nm low power enhanced (8LPU) CMOS device technology
    • 1.8V±5%, 1.2V±5%, 0.75/0.85V±5% power supply
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 8nm
  • GF 22FDX combo voltage regulator combining a high efficiency DC-DC for operation in normal mode and an ultra-low quiescent uLDO to supply AON domain during sleep mode
    • Perfect fit for battery-powered IoT applications that require both high-efficiency during active mode and ultra-low power consumption in AON domain during sleep and deep sleep mode
    • Support of input voltage from 1.9 V to 5.5 V (Li-Ion, USB supplies)
    • Embedded RCU (Regulator Control Unit) to manage booting and mode transitions and to ensure data integrity
    • Configurable output current to fit the application
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