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DDR2 IP

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Search (253)
Compare 253 IP from 29 vendors (1 - 10)
  • DDR2 Monitor Verification IP
    • Supports DDR2 memory devices from all leading vendors
    • Quickly validates the implementation of the DDR2 standard
    • Constantly monitors DDR2 behavior during simulation
    • Checks for following
    Block Diagram -- DDR2 Monitor Verification IP
  • DDR2 Synthesizable Transactor
    • Supports 100% of DDR2 protocol standard JESD79-2F
    • Supports all the DDR2 commands as per the specs
    • Supports double data rate interface
    • Supports up to 4 GB device density
    Block Diagram -- DDR2 Synthesizable Transactor
  • DDR2 DFI Verification IP
    • Compliant with DFI version 2.0 or higher Specification.
    • DFI-DDR2 Applies to :
    • DDR2 protocol standard JESD79-2F Specification
    • Supports all Interface Groups.
    Block Diagram -- DDR2 DFI Verification IP
  • DDR2 Memory Model
    • Supports DDR2 memory devices from all leading vendors.
    • Supports 100% of DDR2 protocol standard JESD79-2F.
    • Supports all the DDR2 commands as per the specs.
    • Supports double data rate interface.
    Block Diagram -- DDR2 Memory Model
  • DDR2 DFI Assertion IP
    • Specification Compliance
    • Compliant with DFI version 2.0 or higher Specification.
    • DFI-DDR2 Applies to :
    • DDR2 protocol standard JESD79-2F Specification
    Block Diagram -- DDR2 DFI Assertion IP
  • DDR2 Assertion IP
    • Specification Compliance
    • Compliant with DDR2 specifications.
    • Supports all DDR2 data widths and address widths.
    • Supports all DDR2 bank address widths.
    Block Diagram -- DDR2 Assertion IP
  • DDR2 Controller IIP
    • Supports DDR2 protocol standard JESD79-2F Specification.
    • Compliant with DFI-version 2.0 or higher Specification.
    • Supports all the DDR2 commands as per the specs.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    Block Diagram -- DDR2 Controller IIP
  • Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
    • Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
    • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
    • Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
    Block Diagram -- Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
  • Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
    • Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
    • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
    • Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
    Block Diagram -- Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
  • DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
    • Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
    • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
    • Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
    Block Diagram -- DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
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