DDR2 Synthesizable Transactor

Overview

Key Features

• Supports 100% of DDR2 protocol standard JESD79-2F
• Supports all the DDR2 commands as per the specs
• Supports double data rate interface
• Supports up to 4 GB device density
• Supports 8 internal banks
• Supports following devices:
  • X4
  • X8
  • X16
• Supports all speed grades as per specification
• Supports programmable Write latency and read latency
• Supports programmable burst lengths: 4,8
• Supports following burst types:
  • Sequential
  • Interleave
• Supports burst sequence
• Checks for following:
  • Check-points include power up,initialization and power off rules
  • State based rules, active Command rules
  • Read/Write command rules etc
  • All timing violations
• Supports all mode registers programming
• Supports extended mode registers programming
• Supports write data mask
• Supports power down features
• Supports self refresh mode
• Supports auto precharge option for each burst access
• Supports ODT(On-Die Termination)
• Supports DLL
• Supports full-timing as well as behavioral versions in one model
• Supports all timing delay ranges in one model: min, typical and max
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Benefits

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

Block Diagram

Deliverables

• Synthesizable transactors
• Complete regression suite containing all the DDR2 testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes

Technical Specifications