IP Catalog > Capture Engine

Capture Engine IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (13)
Compare 13 IP from 7 vendors (1 - 10)
  • Lancero Scatter-Gather DMA Engine for PCI Express
    • PCIe I/O performance: 200 MB/s x1 Gen 1 up to 3360 MB/s x8 Gen 2
    • Easily connect logic and high-speed I/O peripherals to PCI Express
    • Target Bridge supports Avalon Memory Mapped custom logic
    • SGDMA Engine supports Avalon Streaming burst access devices
    Block Diagram -- Lancero Scatter-Gather DMA Engine for PCI Express
  • Camera capture unit for multi-camera systems
    • Down-scaling
    • De-interlacing
    • Histogram measurement
  • 100G OTN Digital Wrapper
    • Transmit Processing
    • Receive Processing
    • Alarms and Errors
    • The following OTU layer alarms and errors are detected :
    Block Diagram -- 100G OTN Digital Wrapper
  • 40G OTN Digital Wrapper
    • Transmit Processing
    • Receive Processing
    • Alarms and Errors
    • The following OTU layer alarms and errors are detected :
    Block Diagram -- 40G OTN Digital Wrapper
  • 10G OTN Digital Wrapper
    • Transmit Processing
    • Receive Processing
    • Alarms and Errors
    • The following OTU layer alarms and errors are detected :
    Block Diagram -- 10G OTN Digital Wrapper
  • 2.5G OTN Digital Wrapper
    • Transmit Processing
    • Receive Processing
    • Alarms and Errors
    • The following OTU layer alarms and errors are detected :
    Block Diagram -- 2.5G OTN Digital Wrapper
  • IP platform for intelligence gathering chips at the Edge
    • High performance IoT solutions for AI at the Edge can now be created up to 30% faster
    Block Diagram -- IP platform for intelligence gathering chips at the Edge
  • ISDB-T Demodulator
    • Full 13-segment ISDB-T demodulator
    • ARIB STD-B31 compliant supporting 1, 2 or 3-layers
    • High-performance demodulation engine for demanding applications
    • Sophisticated channel impairment correction
  • DDR-I/II/III CONTROLLER IP CORE
    • Compliant with JEDEC Standard.
    • Support up to 4 Gb and 8 banks of DDR2 devices.
    • Application bus – FIFO, AHB, Avalon. Support multiple agents on application bus interface with built-in credit/aging based weighted round robin arbitration scheme.
    • Programmable CAS latency and DRAM timing parameters.
    Block Diagram -- DDR-I/II/III CONTROLLER IP CORE
  • LPDDR5/4/4X PHY in Samsung (14nm) for Automotive
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR5 SDRAMs up to 6400 Mbps
    • Compatible with JEDEC standard LPDDR4 and LPDDR4X SDRAMs up to 4267 Mbps
    • DFI 5.0 compliant interface to the memory controller
×
Semiconductor IP