IP Catalog > Arrow Devices

Arrow Devices IP

Filter
Filter

Login required.

Sign in

Search (12)
Compare 12 IP from 10 vendors (1 - 10)
  • Highly configurable high-speed serial link controller
    • SpaceFibre codec designed according to the SpaceFibre specification ECSS-E-ST-50-11C, single-lane implementation
    • WizardLink codec designed to interface with Texas Instrument TLK2711 transceiver
    • The IP can inter-operate with off-chip SerDes devices or with FPGA/ASIC hard macros
    • Optional 8b10b encoding
    Block Diagram -- Highly configurable high-speed serial link controller
  • Quad SPI Master IP
    • Compliant with AMBA AXI3/4 and AXI4-lite protocols.
    • User configurable clock frequency support
    • Designed to support all leading NOR FLASH devices.
    Block Diagram -- Quad SPI Master IP
  • SAS INITIATOR IIP
    • Supports SPL 1.0/2.0/3.0/4.0/5.0 Specs
    • Fully synthesizable
    • Static synchronous design
    • Positive edge clocking and no internal tri-states
    Block Diagram -- SAS INITIATOR IIP
  • PCIe Controller for USB4 with AXI
    • Internal data path size automatically scales up or down (64-, 256-, 512- bits) based on link max. speed and width for reduced gate count and optimal throughput
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code – Gen5 support pending
    • Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
    • Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces
    Block Diagram -- PCIe Controller for USB4 with AXI
  • Normal Speed PSRAM Solution
    •  AXI3/AHB and APB3 bus interfaces
    •  AXI narrow/unaligned transfer, and AHB narrow transfer
    •  AXI burst supports INCR and WRAP
    •  AHB burst supports SINGLE, INCR, INCR4/8/16, WRAP4/8/16
    Block Diagram -- Normal Speed PSRAM Solution
  • Ultra low power inference engine
    • Neuromorphic processor
    • Sub milliwatt power
    • Ultra-low power AI processing
    Block Diagram -- Ultra low power inference engine
  • xSPI Master IP | NOR IP
    • JESD 251 compliant
    • JEDEC SFDP Compliant
    Block Diagram -- xSPI Master IP | NOR IP
  • SAS Initiator, 12G, 4 Ports, 48 Gbps
    • The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devices.
    • Maximum supported bandwidth is 48 Gbps. The serial link employs multiple high-speed gigabit transceivers.
    Block Diagram -- SAS Initiator, 12G, 4 Ports, 48 Gbps
  • DO-254 External Memory Controller 1.00a
    • Supports AXI4 specification for AXI interface
    • Full AXI4 slave interface supports 32-bit address bus and 32/64-bit data bus
    • Supports 32-bit configurable AXI4-Lite control interface to access internal registers
    • Supports Burst transfers of 1-256 beats for INCR burst type and 2, 4, 8, 16 beats for WRAP burst type
  • AXI External Memory Controller
    • Supports AXI 4 specification for AXI interface
    • Full AXI Slave interface supports 32- Bit Address bus and 32/64-bit data bus
    • Supports 32-Bit configurable AXI4 Lite control interface to access internal registers
    • Supports Burst transfers of 1-256 beats for INCR burst type and 2, 4, 8, 16 beats for WRAP burst type
×
Semiconductor IP