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Achronix IP

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  • Embedded FPGA
    • 75% lower power
    • 90% lower cost
    • 100× lower latency
    Block Diagram -- Embedded FPGA
  • Chacha20-Poly1305 IP for FPGA and ASIC
    • Available in 2 versions:
    • Fast : High bandwith with low latency and high frequency
    • Small : Higher latency but smaller footprint
    • Full standard support : Zyxx ChaCha20-Poly1305 supports full specification of the ChaCha20-Poly1305 standard
  • Configurable Ascon IP for FPGA and ASIC
    • Available in different configurations :
    • ? Ascon-128 for authenticated encryption with 64 bits data blocks
    • ? Ascon-128a for authenticated encryption with 128 bits data
    • blocks
  • Virtualized Accelerator Engine
    • Ultra-High-Speed Search Engine IP
    • Deep Header Inspection (DHI) solution
    • Uses MoSys Graph Memory Engine (GME)
  • Polar Encoder / Decoder for 3GPP 5G NR
    • Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
    • Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
    • High error correction performance from Polar PC/CRC-aided decoder core
    • Tightly integrates the components in the chain to reduce area usage and latency
    Block Diagram -- Polar Encoder / Decoder for 3GPP 5G NR
  • LDPC Encoder / Decoder for 3GPP 5G NR
    • Fully compliant with the 3GPP NR standard for PDSCH, PUSCH. Supports the full range of uncoded and encoded block sizes
    Block Diagram -- LDPC Encoder / Decoder for 3GPP 5G NR
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