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Achronix IP

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Compare 5 IP from 4 vendors (1 - 5)
  • Embedded FPGA
    • 75% lower power
    • 90% lower cost
    • 100× lower latency
    Block Diagram -- Embedded FPGA
  • Chacha20-Poly1305 IP for FPGA and ASIC
    • Available in 2 versions:
    • Fast : High bandwith with low latency and high frequency
    • Small : Higher latency but smaller footprint
    • Full standard support : Zyxx ChaCha20-Poly1305 supports full specification of the ChaCha20-Poly1305 standard
  • Configurable Ascon IP for FPGA and ASIC
    • Available in different configurations :
    • ? Ascon-128 for authenticated encryption with 64 bits data blocks
    • ? Ascon-128a for authenticated encryption with 128 bits data
    • blocks
  • Virtualized Accelerator Engine
    • Ultra-High-Speed Search Engine IP
    • Deep Header Inspection (DHI) solution
    • Uses MoSys Graph Memory Engine (GME)
  • Polar Encoder / Decoder for 3GPP 5G NR
    • The patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.
    • The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance.
    Block Diagram -- Polar Encoder / Decoder for 3GPP 5G NR
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Semiconductor IP