ChaCha20-Poly1305 is an AEAD algorithm based on the very fast ChaCha20 stream cipher with the Poly1305 MAC. It was proposed by It is standardized in the RFC 84391 and is widely used in TLS 1.2, TLS 1.3, SSH, Wiregard…
Chacha20-Poly1305 IP for FPGA and ASIC
Overview
Key Features
- Available in 2 versions:
- Fast : High bandwith with low latency and high frequency
- Small : Higher latency but smaller footprint
- Full standard support : Zyxx ChaCha20-Poly1305 supports full specification of the ChaCha20-Poly1305 standard
- AXI4 compatible interface can be added as an option
- Available for a wide range of FPGA vendors : AMD (Xilinx), Intel (Altera), Microchip, Lattice, Achronix, QuickLogic.
- Available for Asics
Benefits
- Lowest footprint on the market
Deliverables
- Netlist, sourcecode
Technical Specifications
Short description
Chacha20-Poly1305 IP for FPGA and ASIC
Vendor
Vendor Name
Foundry, Node
On demand
Related IPs
- Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
- Verification IP for CAN XL, FD and CAN 2.0
- Multi-channel codec to ASIC / FPGA
- Cryptographic library for Elliptic Curve Diffie–Hellman (ECDH) and Elliptic Curve Digital Signature Algorithm (ECDSA)
- Hardware accelerator for RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- Multi-Channel Flex DMA IP Core for PCI Express