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AMBA Multi-Channel DMA Controller IP

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  • AXI4 Multi-Channel DMA Controller
    • 1 - 16 Multi-Channel High Performance DMA Controller Engines:
    • Up to 16 DMA transfers in parallel active
    • Hardware or Software Initiated Transfers
    • Link-List Processor for Autonomous & Chained Block Transfers
  • AHB Multi-Channel DMA Controller
    • 1 - 16 Multi-Channel High Performance DMA Controller Engines:
    • High-Speed Finite State Machine Control
    • High Throughput to/from Memory & Peripherals via AMBA AHB on both small and large data sets
    • Configurable with Dual-Port, Single- or Dual-Clock FIFO
  • DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
    • 2 Dedicated DMA Channels, 1 each for data transfers for the following:
    • Command and Status via AXI4-Stream Interfaces - 1 set per MM2S & S2MM:
    • MM2S & S2MM DMA Controllers:
    • Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
    Block Diagram -- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
  • DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
    • 2 Dedicated DMA Channel
    • Command and Status via Scatter Gather List (SGL)
    • Arbiter – Round Robin
    Block Diagram -- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
  • RapidIO to AXI Bridge (RAB)
    • Compliant with RapidIO specification, Revision 4.0
    • Compliant to AMBA AXI protocol v4
    • Supports 32-bit or 38-bit addressing
    • AXI PIO operation with configurable number of AXI Slaves
    Block Diagram -- RapidIO to AXI Bridge (RAB)
  • PCIe DMA Controller (Low Latency)
    • Implements standard Transaction layer functions e.g. TLP generation/reception, TLP completion handling and interrupt generation
    • Implements 32-bit, 64-bit, 128-bit and 256-bit User application. (Width selection is based on PCIe endpoint interface width)
    • PCIe Gen1, Gen2 and Gen3 support.
    • Up to 8 independent DMA channels with each channel capable of operating in Block-DMA or Scatter-Gather DMA modes
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Semiconductor IP