The DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with user selectable AMBA AXI4 / AXI3 Master Read/Write interconnects. The DB-DMAC-MC-AXI excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, 16. Please contact the vendor about our configurable DB-DMAC-MC-AXI with 1 to 256 DMA Channels.
SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces
Overview
Key Features
- 1 - 16 Multi-Channel High Performance DMA Controller Engines:
- High-Speed Finite State Machine Control
- High Throughput to/from Memory & Peripherals via AMBA AXI4 / AXI3 on both small and large data sets
- Dual-Port, Dual-Clock FIFO, user parameterized in Depth x Width
- Optional Dual-Port, Single-Clock FIFO design
- Up to 16 DMA transfers in parallel active
- Hardware or Software Initiated Transfers
- Link-List Processor for Autonomous & Chained Block Transfers
- Scatter / Gather – supports non-contiguous data block transfers to a contiguous segment of memory and vice versa
- Arbiter with variety of Arbitration Modes including Quality of Service (QoS) and low-latency
- Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024. Data re-alignment matching interfaces with different data widths
- Programmable Data Burst Capability: 1, 4, 8, 16 on AXI4/AXI3 Interfaces. Up to 256 on AXI4
- Interrupt Controller – Signaling DMA Transfer Done & Diagnostics
- AXI DMA Backbone or PCIe DMA Engine
- Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.
Block Diagram
Deliverables
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Technical Specifications
Related IPs
- SG DMA Controller, 1-16 DMA Channels, AHB5 Master Interface
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- AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
- AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP
- AXI4 to/from AXI4-Stream Scatter-Gather DMA
- AXI4 Memory-Mapped to/from AXI4-Stream DMA