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AMBA 5 CHI IP

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Compare 22 IP from 9 vendors (1 - 10)
  • AMBA 5 CHI Verification IP
    • VIP is Compliant with the latest ARM™ AMBA5 CHI.
    • Support any type of network topology like Crossbar, Ring, Mesh, etc…
    • Support for all types of AMBA5 CHI Nodes:
      • Requester (RN-F, RN-D, RN-I)
      • Home (HN-F, HN-I)
      • Subordinate (SN-F, SN-I)
    • Requester (RN-F, RN-D, RN-I)
    Block Diagram -- AMBA 5 CHI Verification IP
  • AMBA 5 CHI Verification IP
    • Compliant with the latest ARM AMBA 5 CHI specification (CHI-D).
    • Supports CHI Master, Slave, Interconnect, Monitor and Checker.
    • Support for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links.
    • Supports all CHI protocol node types:
    Block Diagram -- AMBA 5 CHI Verification IP
  • AMBA 5 CHI Synthesizable Transactor
    • Compliant with the latest ARM AMBA 5 CHI specification (CHI-B).
    • Supports CHI Master, Slave, Interconnect.
    • Support for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links.
    • Supports all CHI protocol node types:
    Block Diagram -- AMBA 5 CHI Synthesizable Transactor
  • AMBA 5 CHI Assertion IP
    • Specification Compliance
    • Compliant with the latest ARM AMBA 5 CHI specification.
    • Supports all ARM AMBA 5 CHI data widths.
    • Supports for Protocol, Network and Link layer communication, including flow control mechanisms across RN2HN and HN2SN links.
    Block Diagram -- AMBA 5 CHI Assertion IP
  • AMBA 5 CHI Verification IP
    • VIP is Compliant with the latest ARM™ AMBA5 CHI.
    • Support any type of network topology like Crossbar, Ring, Mesh, etc…
    • Support for all types of AMBA5 CHI Nodes:
      • Requester (RN-F, RN-D, RN-I)
      • Home (HN-F, HN-I)
      • Subordinate (SN-F, SN-I)
    • Requester (RN-F, RN-D, RN-I)
    Block Diagram -- AMBA 5 CHI Verification IP
  • Simulation VIP for AMBA CHI
    • Transaction type
    • Monitoring and driving of all protocol Opcodes
    • Dummy interconnect
    • Dummy CHI-based interconnect support. When interconnect is not present, the Active Hn-F can generate snoop requests and respond to Rn-F commands
    Block Diagram -- Simulation VIP for AMBA CHI
  • NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
    • Easy to integrate the NoC Silicon IP using interface
    • N master and M slave ports based on customer requirement
    • Supports wide range of memory map.
    Block Diagram -- NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
  • Tessent NoC Monitor
    • Full transaction and trace-level visibility of traffic
    • Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
    Block Diagram -- Tessent NoC Monitor
  • Coherent Mesh Network
    • High-Performance, Scalable Coherent Mesh
    • Reduce SoC Integration Time
    • Maximize Compute Density
    • Coherent Multichip Links
  • Tessent in-life monitoring
    • Bus Monitor enables complete, transaction-level visibility of SoC bus activity across all major standards (AXI, ACE, OCP)
    • Network-on-Chip (NOC) Monitor provides transaction-level visibility for devices using the Arm AMBA 5 Coherent Bus Interface (CHI)
    • Status Monitors provides embedded logic analyzer capability
    • Processor Analytics provides run-control, performance monitoring, cross triggering, and event driven control of embedded processors.
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