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AHB Cache controller IP

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Compare 42 IP from 10 vendors (1 - 10)
  • AHB Cache Controller
    • The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master interface to the memory subsystem. The processor and memory interfaces are natively AHB5 and can easily be reduced to AHB-lite. 
    • The cache controller core supports a four-way associative cache memory and implements a Least Recently Used (LRU) replacement policy.
    Block Diagram -- AHB Cache Controller
  • 64-bit CPU Core with Level-2 Cache Controller
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    • DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
    • Andes extensions, architected for performance and functionality enhancements
    • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
    Block Diagram -- 64-bit CPU Core with Level-2 Cache Controller
  • eMMC 4.51 Device Controller IP
    • Compliant to JEDEC JESD84-B45 eMMC 4.51 spec
    • Packed commands for faster processing
    • Supports cache control mechanism
    • Supports eMMC4.51 Security Protocol Commands
    Block Diagram -- eMMC 4.51 Device Controller IP
  • ONFI 2 NAND Flash Controller IP Compliant to JEDEC
    • The ONFI 2.3 NAND Flash Controller IP Core is a full-featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development.
    • Designed to support both SLC and MLC flash memories, ONFI 2.3 NAND controller IP is flexible in use and easy in implementation.
    Block Diagram -- ONFI 2 NAND Flash Controller IP Compliant to JEDEC
  • MIPI LLI Controller
    • The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory.
    • This is achieved by the low latency from the “companion” chip to the memory interface of the host chip.
    Block Diagram -- MIPI LLI Controller
  • CXL CONTROLLER IIP
    • Compliant with CXL 1.0/1.1 Specifications
    • Supports Native PCIe mode and below features as defined in the PCIe specification
    • PCIE Express specs 1.0/2.0/3.0/4.0/5.0
    • PIPE interface
    Block Diagram -- CXL CONTROLLER IIP
  • Compact High-Speed 32-bit CPU Core with Level-2 Cache
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    • DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
    • Andes extensions, architected for performance and functionality enhancements
    Block Diagram -- Compact High-Speed 32-bit CPU Core with Level-2 Cache
  • AHB Secure Subsystem - ARM Cortex M3
    • The Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software security.
    • It integrates a security-conscious processor, the ARM Cortex-M3, with a security-conscious low power high-performance subsystem.
    • Everything is pre-integrated with the necessary AHB and APB IP cores needed to run a small software kernel or a Real Time Operating System (RTOS).
    Block Diagram -- AHB Secure Subsystem - ARM Cortex M3
  • 32-Bit SPARC V8 Processor
    • SPARC V8 instruction set with V8e extensions and compare-and-swap
    • Advanced 7-stage dual-issue pipeline
  • RISC-V Application Processor
    • The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture.
    • The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel.
    Block Diagram -- RISC-V Application Processor
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Semiconductor IP