ADAS IP
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193
IP
from 24 vendors
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10)
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Image Signal Processing for ADAS and Display Applications
- Multi-Camera Support
- Advanced Image Processing
- Every Pixel Reliable
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Single channel ADAS chip with FuSa monitor
- The SFA 250A has been designed to be easy to adapt to suit the support needs of the customer’s IP as it is scalable, both in terms of function and performance, as well as modular as multiple versions can be combined to form larger solutions.
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Quad channel ADAS IP platform
- Can cut design cost and time to market by up to 30%.
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Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
- The only Multi-Threaded Out-of-Order RISC-V Core with ASIL-B Certification
- Highly scalable multi-core, multi-cluster, coherent computing solution
- MIPS extensions for improved performance and functionality
- Use in Automotive, Datacenter, and Embedded applications
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Embedded Hardware Security Module (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
- The RT-64x Embedded Hardware Security Module (Root of Trust) family are fully programmable, ISO 26262 ASIL-B hardware security cores offering security by design for automotive applications.
- They protect against a wide range of failures such as permanent, transient and latent faults and hardware and software attacks with state-of-the-art anti-tamper and security techniques.
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FlexRay - High-speed, reliable communication for safety-critical systems
- FlexRay is a high-speed communication protocol designed for time-critical automotive and industrial applications. It ensures reliable, fault-tolerant communication, essential for safety-critical systems like ADAS, powertrains, and chassis control.
- FlexRay Verification IP (VIP) ensures compliance with FlexRay standards, simulating message transmission, scheduling, error detection, fault tolerance, and real-time synchronization across nodes. This testing ensures system reliability and reduces design flaws during development.
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AI inference engine for real-time edge intelligence
- Flexible Models: Bring your physical AI application, open-source, or commercial model
- Easy Adoption: Based on open-specification RISC-V ISA for driving innovation and leveraging the broad community of open-source and commercial tools
- Scalable Design: Turnkey enablement for AI inference compute from 10’s to 1000’s of TOPS
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MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
- Support CSI2, DSI2, I2C, GPIO,eDP/DP, and SPI as Protocols later
- For Functional safety, CSE & DSE are supported
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GDDR7 PHY
- Highest performance at 36Gbp/s
- Fully hardened timing-closed PHY
- Available in multiple advanced-process nodes
- PAM3 signaling or NRZ
- 4 independent channels
- PHY independent mode
- Microcontroller or state machine training
- Low-power clock gating
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Ethernet TSN Endstation Controller IP for Automotive
- Fully integrated hardware and software solution
- One physical Ethernet port and dedicated host port
- Seamless integration with host CPU or external micro-controller
- Time synchronization as per IEEE 802.1AS with grandmaster and slave support