40G MAC/PCS ULL IP

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Compare 162 IP from 31 vendors (1 - 10)
  • XLGMII 40G Ethernet Verification IP
    • Follows XLGMII specification as defined in IEEE 802.3ba
    • Supports all types of XLGMII TX and RX errors insertion/detection
    • Oversize, undersize, inrange, out of range Packet size errors
    • Missing SPD/EPD/SFD framing errors
    Block Diagram -- XLGMII 40G Ethernet Verification IP
  • Ethernet 40G,100G Verification IP
    • Supports 1G
    • Supports GMII
    • Supports TBI (i.e Output of 8b/10b PCS)
    • Supports SGMII(10M/100M/1000M) as per specification 1.8
    Block Diagram -- Ethernet 40G,100G Verification IP
  • Ethernet 40G Synthesizable Transactor
    • Supports 40G as per 802.3ba:
    • Supports XLGMII
    • Supports 40GBase-KR4/40GBase-CR4/40GBase-SR4/40GBase-LR4
    • Supports 40GBase-R
    Block Diagram -- Ethernet 40G Synthesizable Transactor
  • Ethernet 40G,100G Verification IP
    • Provides 40G as perIEEE standard 802.3-2018 specification
      • Supports Ethernet XLGMII
      • Supports FEC, PCS, AN, and XLAUI
      • Supports KR4 & Cr4
    • Supports Ethernet XLGMII
    • Supports FEC, PCS, AN, and XLAUI
    • Supports KR4 & Cr4
    Block Diagram -- Ethernet 40G,100G Verification IP
  • 40G UDP IP Stack
    • 40G Ethernet
    • IPv4 support without packet fragmentation
    • Jumbo Frames
    • Transmit and Receive
    Block Diagram -- 40G UDP IP Stack
  • V-by-One Rx IP, Silicon Proven in 40G
    • Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
  • V-by-One Tx IP, Silicon Proven in 40G
    • Wide-range data rate, up to 1Gbps, the associated
    • clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
  • 40G OTN Processor, Transponder
    • 4 Client Ports support up to 40G of traffic presented through 4 multi-rate and multi-protocol interfaces. The 10G-class Client Signals can be accepted through serial or parallel interfaces.
    • 4 Client Signal Processors, each capable of supporting up to 10G of Client Traffic, implement the functionality of various Client-Side protocols, such as Ethernet, SDH/SONET, OTN and more.
    • A Transparent Agnostic Fabric (TAF) provides non-blocking, unidirectional, bi-directional and unrestricted multicast connectivity.
    • 4 Line Signal Processors, each capable of supporting up to 10G of Line Traffic, implement the functionality of OTU2 bearers offering multiple choices of Forward Error Correction (FEC) algorithms. The 4 OTU2 signals can be presented over serial or parallel SFI4.2 interfaces.
    Block Diagram -- 40G OTN Processor, Transponder
  • 40G OTN Processor, Muxponder
    • 16 Client Ports support up to 40G of traffic presented through 16 multi-rate and multi-protocol interfaces.
    Block Diagram -- 40G OTN Processor, Muxponder
  • OTN Framer
    • Single chip FPGA architectures, highly efficient resource sharing with no fitting issues.
    • 200MHz+ push button performance with no timing closure issues.
    • All products designed from ground up to allow future datapath & channel scaling.
    • Enabling migration path to 100G solutions with 43G throughput today.
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