V-by-One Tx IP, Silicon Proven in 40G
Overview
The V-by-One HS technology aims to transmit video signals at a high data rate using an internal connection between devices. The requirements to create a transmitter and receiver are laid out in the V?by-One® HS Standard. This has an available 8-lane PHY and 16-lane PHY for Tx and Rx, and it supports up to 4Gbps/lane.
Key Features
- Wide-range data rate, up to 1Gbps, the associated
- clock is DDR clock (1/2 of the data rate, up to 500MHz)
- 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
- DC coupling mode
- Multi-channel shared offset
- Built-in transmitter terminal impedance, no need for off-chip components
- Support AXI stream bus protocol and data transceiver
- Built-in self-test mechanism, which can independently complete feature and mass production testing
- Support link training mode
- Support Flip-chip package form
- ESD: HBM/MM/CDM/Latch-Up 2000V /200V /500V/ 100mA
- Silicon Proven in TSMC 40G
Deliverables
- Datasheet
- Integration guideline
- GDSII or Phantom
- GDSII Layer map table
- CDL netlist for LVS
- LEF Verilog behaviour model
- Liberty timing model DRC/LVS/ERC results
Technical Specifications
Maturity
In Production
Availability
Immediate
Related IPs
- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
- V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
- V-by-One/LVDS Tx Combo PHY, Silicon Proven in 28HPC+
- HDMI 2.0 Tx PHY & Controller IP, Silicon Proven in ST 28FDSOI