Ethernet 40G Synthesizable Transactor

Overview

The Ethernet 40G Synthesizable Transactor verifies Ethernet interfaces. Ethernet is build on top of it to make it robust. Ethernet 40G Synthesizable Transactor provides a smart way to verify the Ethernet component of a SOC or a ASIC in Emulator or FPGA platform. Ethernet 40G Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Key Features

Supports 40G as per 802.3ba:

Supports XLGMII
Supports 40GBase-KR4/40GBase-CR4/40GBase-SR4/40GBase-LR4
Supports 40GBase-R
Supports 40GBase-KR2
Supports FEC
Supports scrambler
Supports backplane auto-negotiation

Supports Mac control and data frames support
Ability to generate VLAN tagged and Priority tagged frames
Supports Pause frame detection and generation
Supports Jumbo frames
Supports Under and oversize frame
PCS to serdes interface supports all widths
Full support for IEEE 1588-2002 and IEEE 1588-2008
Supports all types of TX and RX errors insertion/detection at each layer

Supports Under and oversize frame
CRC errors
Framing errors
Pause frame errors
Disparity and Auto-negotiation errors
Invalid code group insertion
Lane Skew insertion
Invalid AN sequence error insertion

Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations

Benefits

Compatible with testbench writing using SmartDV's VIP
All UVM sequences/testcases written with VIP can be reused
Runs in every major emulators environment
Runs in custom FPGA platforms

Block Diagram

Deliverables

Synthesizable transactors
Complete regression suite containing all the Ethernet testcases
Examples showing how to connect various components, and usage of Synthesizable Transactor
Detailed documentation of all DPI, class, task and functions used in verification env
Documentation contains User's Guide and Release notes

Technical Specifications

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