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3GPP IP

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Compare 99 IP from 29 vendors (1 - 10)
  • PDSCH Encoder for 3GPP 5G NR
    • The PDSCH Encoder and PUSCH Decoder products simplify the creation of high performance 5G NR implementations.
    • PDSCH Encoder features the new QAM mapper and Scrambler functionality. These are integrated with LDPC encoder chain and transport block chain components.
    • PDSCH encoder has a configurable IQ parallelism for improved performance per clock.
    • The functions included are CRC, Segmentation, LDPC encode, Rate matching, Integrated HARQ, Concatenation, Scrambling and Modulation.
    Block Diagram -- PDSCH Encoder for 3GPP 5G NR
  • Polar Encoder / Decoder for 3GPP 5G NR
    • Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
    • Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
    • High error correction performance from Polar PC/CRC-aided decoder core
    • Tightly integrates the components in the chain to reduce area usage and latency
    Block Diagram -- Polar Encoder / Decoder for 3GPP 5G NR
  • LDPC Encoder / Decoder for 3GPP 5G NR
    • Fully compliant with the 3GPP NR standard for PDSCH, PUSCH. Supports the full range of uncoded and encoded block sizes
    Block Diagram -- LDPC Encoder / Decoder for 3GPP 5G NR
  • PUSCH Decoder for 3GPP 5G NR
    • Complete implementation of the relevant 3GPP standard
    • Improved BLER for UCI control data
    Block Diagram -- PUSCH Decoder for 3GPP 5G NR
  • PUSCH Equalizer for 3GPP 5G NR
    • Complete implementation of the relevant 3GPP standards
    • Improved spectral efficiency across low SINR range against industry-standard simulation toolbox
    Block Diagram -- PUSCH Equalizer for 3GPP 5G NR
  • Ultra-Compact 3GPP Cipher Core
    • Keystream generation using the ZUC Algorithm version 1.6 (ZUC-2011)
    • High throughput: up to 40 Gbps in 65 nm process, 10 Gbps in Altera Stratix III
    • Small size: from 7.5K ASIC gates
    • Satisfies ETSI SAGE ZUC and EAE3/EIA3 specifications
    Block Diagram -- Ultra-Compact 3GPP Cipher Core
  • WCDMA Release 9 compliant Viterbi Decoder
    • 3GPP TS 25.212 V 9.5.0 Release 9
    • Supports all block sizes i.e., K=40 - 504.
    • Constraint length of 9
    Block Diagram -- WCDMA Release 9 compliant Viterbi Decoder
  • High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
    • 3GPP LTE/ LTE A compliant
    • Implements decoder for requirements as defined in Section 5.1.3.2 of the specification
    Block Diagram -- High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
  • Complete FEC Encoder Solution compliant to LTE/ LTE A Specification
    • Controlled selection of Turbo or Convolution path (based on data blocks input or control data input)
    • Rate 1/3 tail biting Convolution encoder
    • Rate 1/3 turbo encoder
    • Rate matching for Turbo coded transport channels
    Block Diagram -- Complete FEC Encoder Solution compliant to LTE/ LTE A Specification
  • Very High Speed 3GPP LTE Turbo Decoder
    • 8 state 3GPP LTE compatible turbo decoder
    • Rate 1/3
    • 40 to 6144 bit interleaver
    • Up to 280 MHz internal clock
    Block Diagram -- Very High Speed 3GPP LTE Turbo Decoder
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