2D Graphic Engine IP

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Compare 17 IP from 6 vendors (1 - 10)
  • 2D Graphics Hardware Accelerator (AHB Bus)
    • Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
    • Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
    • Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
    • Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
    Block Diagram -- 2D Graphics Hardware Accelerator (AHB Bus)
  • 2D Graphics Hardware Accelerator (AXI Bus)
    • Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
    • Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
    • Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
    • Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
    Block Diagram -- 2D Graphics Hardware Accelerator (AXI Bus)
  • 2D Blit and Raster Graphics
    • All buffer formats 100% compatible
    • Flexible pixel formats (1/2/4/8/16/18/24/32 bpp; any bit width per channel)
    • YUV support (packed, planar, 4:4:4, 4:2:2, 4:2:0, progressive, interlaced)
    • Dynamic re-configuration of processing units
  • Advanced 2D Graphics Controller
    • Fully synchronous, synthesizable and technology independent RTL code
    • Capable of drawing shapes such as pixels, lines and rectangles
  • 2D Graphics Hardware Accelerator (AXI4 Bus)
    •  Generates bitmaps from graphics instructions as well as combining existing  bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations  
    •  Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit  
    •  Performs Alpha Blend operations of bitmaps with its Alpha Blend unit  
    •  Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit  
    Block Diagram -- 2D Graphics Hardware Accelerator (AXI4 Bus)
  • High-performance 2D (sprite graphics) GPU IP combining high pixel processing capacity and minimum gate count.
    • GH310 is a GPU IP that packages the 2D Sprite engine available in the GSHARK-TAKUMI family IPs. This IP accelerates 2D graphics on embedded systems such as digital audio-video devices.
    • Casting no LSI cost impact with the smallest-in-family footprint (gate count), GH310 helps enrich your displays including GUIs instantly and easily.
  • 2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
    • Vertically integrated HW + SW solution
    • Monolithique HW building block, open to any system integration. Can be associated with any companion IP:
    • 2 hardware versions:
    • Software ported on numerous processors and OS
  • 3D OpenGL ES GPU (Graphics Processing Unit)

     

    • Scalability throughout the entire design
    • Unified Shader Architecture
    • Massively parallel execution with fine grained Multithreading
    • Bandwidth reduction by e.g. on the fly data compression/decompression
    Block Diagram -- 3D OpenGL ES GPU (Graphics Processing Unit)
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Semiconductor IP