112G serdes IP
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9
IP
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PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- PCie Gen 5/6 compliant
- Up to 112G PAM 4 support
- less than 6 pj/bit typical power consumption
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112G Ethernet PHY in TSMC (N7, N5, N3P)
- Optimized for performance, power, and area
- Includes one, two, or four full-duplex PAM-4 transceivers (transmit and receive functions)
- Supports IEEE and OIF standards: IEEE 802.3ck, CEI-112G
- Includes auto-negotiation and link training capabilities – IEEE 802.3 clause 73
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112Gbps XSR SerDes IP on TSMC 5/4nm
- TSMC N5/N4 processes
- Die-to-Die in Multi-chip Modules or Chiplets 128-bits TX/RX digital interface
- Multiple lane RX & TX Macro with integrated PLLs
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112Gbps XSR SerDes IP on TSMC 12nm
- TSMC 12nm
- Die-to-Die in Multi-chip Modules or Chiplets 128-bits TX/RX digital interface
- Multiple lane RX & TX Macro with integrated PLLs
- On chip eye monitor
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112Gbps XSR SerDes IP on TSMC 7/6nm
- TSMC 7nm and 6nm processes
- Die-to-Die in Multi-chip Modules or Chiplets 128-bits TX/RX digital interface
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56Gbps LR SerDes IP on TSMC 16/12nm
- TSMC 16/12nm process
- Area & Power: Please contact us
- 64-bits TX/RX digital interface
- Single Lane RX & TX Macro with Integrated PLLs
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28Gbps LR SerDes IP on TSMC 28nm
- TSMC 28nm process
- Area & Power: Please contact us
- 28G SerDes Technology operates from 1.2G to 30G wide data rate range.
- 32-bits TX/RX digital interface
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28Gbps MR SerDes IP on TSMC 28nm
- TSMC 40nmG process
- Package: flip chip BGA
- 16-bits TX/RX digital interface
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High Speed Ethernet 2/4/8-Lane 200G/400G PCS
- Compliant with the IEEE 802.3bs standard
- 400G PCS available in single, quad or octal port supporting multiple 100G/50G/25G/10G SerDes lanes
- 200G PCS available in single or quad port supporting multiple 100G/50G/25G/10G SerDes lanes
- Designed to be used with Synopsys 400G and 200G Ethernet MAC IP for 400G/200G Ethernet systems
