10G Ethernet IP

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Compare 102 IP from 32 vendors (1 - 10)
  • Ethernet 10G KR Serdes
    • Quad Channel Multi Lane Macro
    • Integrated backplane PCS, PMA layer
    • High-Speed Data Transfer
    Block Diagram -- Ethernet 10G KR Serdes
  • Low-Latency IP 10G Ethernet MAC
    • LeWiz MAC tracks the Ethernet line for link detection
    • On the receiving side, it:
    • On the transmit side, it:
    • Driver Support is available for Linux (Windows and others available based on customer request)
  • ETHERNET 10G XAUI PCS IP
    • Supports IEEE Standard 802.3.2018 Clause 48 for XAUI PCS
    • Supports 8b/10b encoding on each lane to generate code groups in transmit path
    • Supports 10b/8b decoding on each lane to convert received code groups to 32 XGMII data bits and 4 XGMII control bits
    • Supports synchronization of code groups on each lane to determine code group boundaries
  • ETHERNET 10G TSN MAC IP
    • Compliant with IEEE Standard 802.3-2018 Specification - Clause 46
    • Supports Preemption as per IEEE Standard 802.1Qbu and IEEE Standard 802.3br Interspersing Express Traffic
    • Supports timing synchronization as per IEEE Standard 802.1 AS
    • Supports Traffic Scheduling - IEEE Standard 802.1Qbv(Enhancement for Scheduled Traffic) and IEEE Standard 802.1Qav (Credit Based Shaping)
  • ETHERNET 10G MAC IP
    • Compliant with IEEE Standard 802.3-2018 specification
    • Supports full duplex mode of operation
    • Supports Standard 10Gbps Ethernet link layer data
    • Supports XGMII interface operating at 156.23MHz
  • ETHERNET 10G KR PCS IP
    • Supports IEEE Standard 802.3.2018 Clause 49 for Base R PCS
    • Supports 64b/66b encoding and decoding for transmit and receive path
    • Supports data scrambling on the transmit path and descrambling on the receive path
    • Supports gearbox for various XSBI data width
  • 10G Ethernet TSN Subsystem
    • 10G Ethernet MAC/PCS with 802.1CM (802.3br/802.1bu) preemption and interspersed express traffic feature for MAC+PCS/PMA
    • Designed to the 25G Ethernet requirements for 10/25 Gb/s operation specified by IEEE 802.3 Clause 49, IEEE 802.3by, and the 25G Ethernet Consortium
    • Low latency 64-bit 10G Ethernet MAC and BASE-R IP
    • Allows multiple instantiations up to by 4
  • Block Diagram -- 10-Gbps Ultra-Low Latency Ethernet MAC and PCS
  • 1G/10G TCP/IP Hardware Stack
    • Complete TCP/IP Hardware Stack
    • Trouble-Free Operation
    • Easy SoC Integration
    Block Diagram -- 1G/10G TCP/IP Hardware Stack
  • Ethernet Switch 10G
    • Architecture supports a large number of ports
    • Large number of features supported default
    • Ultra-compact size
    Block Diagram -- Ethernet Switch 10G
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Semiconductor IP