Ethernet 10G Verification IP

Overview

The Ethernet 10G Verification IP is compliant with IEEE 802.3 Specification and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a Ethernet 10G interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment.Ethernet 10G verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.

Ethernet 10G Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Ethernet 10G Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports 10G as per specification IEEE 802.3-2018
- Supports XGMII(32 and 64 Width)
- Supports XGMII_R(32 and 64 Width)
- Supports XTBI (i.e Output of 8b/10b PCS)
- Supports XAUI,RXAUI,DXAUI,RXTBI and 10GBASE-KX4
- Supports 10GBASE-KR with scrambler
- Supports FEC for 10GBase-KR
- Supports scrambler
- Supports backplane auto-negotiation for 10GBase-KX4 and 10GBase-KR
Supports USXGMII
- Supports single port USXGMII as per specification 2.5
- Supports multi-port USXGMII as per specification 2.2
XSBI Interface (16-bit)
XSBI Interface (20-bit)
Supports Link training
Supports G.999.1 Interface
Ethernet Verification IP comes with complete UNH Test suite
Supports the Upper layer protocols
Supports IP in IP
Supports Q in Q
Full support for IEEE 802.1AZ (Energy Efficient Ethernet)
Full support for IEEE 1588-2002 and IEEE 1588-2008
PCS to Serdes interface supports all widths
Supports CDR for serial protocols
Supports WAN Interface Sublayer (WIS), type 10GBASE-W
Supports MDIO slave and master model as per Clause 22 and Clause 45
Supports Glitch insertion and detection
Supports all types of TX and RX errors insertion/detection at each layer.
- Under and oversize frame.
- CRC errors
- Framing errors
- Pause frame errors
- Disparity and Auto-negotiation errors
- Invalid code group insertion
- Invalid /K/ characters insertion
- Lane Skew insertion
- Invalid AN sequence error insertion
- Missing /K/ characters for packet boundries.
Comes with Tx BFM, Rx BFM, and Monitor
Monitor supports detection of all protocol violations
Supports Pause frame generation and detection
Built in coverage analysis
Callbacks in master and slave for various events
Status counters for various events in bus

Benefits

Faster testbench development and more complete verification of Ethernet 10G designs.
Easy to use command interface simplifies testbench control and configuration of Ethernet 10G TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the testcases.
Examples showing how to connect various components, and usage of TX,RX BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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