Ethernet MAC 10G SFP

Overview

The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification.

It is designed to be connected to a PCS/PMA IP with only one clock domain.

The Demo design provided enable a ready to use !

Key Features

  • MAC TX Features
    • Transmit data FIFO interface to define the payload data
    • Transmit Status FIFO interface to define if the CRC has to be append or to transmit a Error Control character
    • Transmit Pause interface to ask the MAC TX to transmit a Pause Frame
    • Transmit FIFO RX Pause interface to ask the MAC TX to transmit a - Pause Frame when FIFO RX becomes nearly full
    • Transmit Configuration interface to define the Device Ethernet address, the padding and the Inter Frame Gap
    • Transmit Statistics interface to collect the type of frame transmitted
  • MAC RX Features
    • Receive data FIFO interface to receive the payload data
    • Receive Status FIFO interface to define the feature of the frame received :
    • Receive configuration interface to configure the MAC RX.
    • Hash table interface
    • Receive Statistics interface to collect the type of frame received

Benefits

  • Demo available on the following evaluation board:
    • Xilinx:
      • KC705
      • ZC706
      • VC707
      • KCU105
      • ZCU102
      • ZCU106
    • MICROCHIP
      • POLARFIRE Evaluation-Kit

Block Diagram

Ethernet MAC 10G SFP Block Diagram

Deliverables

  • Source code or Encrypted Code.

Technical Specifications

Maturity
Good
Availability
Now
×
Semiconductor IP