IP Catalog > Processor IP > General Purpose Processor IP > 32-Bit Microprocessor IP > 32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue

32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue

Overview

N200 Series is designed for deeply embedded application with low power and area consumption.

Key Features

  • Support RV32I/EMACB/Zc ISA.
  • 2-stage pipeline, optimized micro-archtecture for power, area & cost efficiency.
  • Support fast interrupt tail-chaining mechanism, vectored interrupt processing
    mode for extremely fast interrupt response, and interrupt preemptions based
    on interrupt levels.
  • Configurable ILM (Instruction Local Memory) and
    DLM (Data Local Memory) with ECC
  • Configurable Instruction-Cache
  • Support NICE.
  •  
  • Full Standard Debug Function with JTAG/cJTAG port.
  • Full Standard RISC-V Toolchain, and Linux/Windows IDE supported

Benefits

  • Low Power
  • RV32I/EMACB/Zc
  • 2-Stage Pipeline
  • Machine, User, Supervisor-Mode
  • Security(PMP, TEE)
  • AHB-Lite
  • RISC-V Standard Debug
  • JTAG & cJTAG
  • Low Latency Interrupt
  • Full Development Toolkit

Block Diagram

32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue Block Diagram

Technical Specifications

Short description
32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue
Vendor
Vendor Name
Request Info

Related IPs

×
Semiconductor IP