SD/eMMC PHY IP

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Compare 46 SD/eMMC PHY IP from 8 vendors (1 - 10)
  • Samsung 8LPU 3.3V SD/eMMC PHY
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- Samsung 8LPU 3.3V SD/eMMC PHY
  • GF 22FDX 1.8V/3.3V SD/eMMC PHY AG2 Platform
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- GF 22FDX 1.8V/3.3V SD/eMMC PHY AG2 Platform
  • Intel 16 SD/eMMC PHY North/South Poly Orientation
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- Intel 16 SD/eMMC PHY North/South Poly Orientation
  • TSMC 22ULL 1.8V/3.3V SD/eMMC PHY AG2
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- TSMC 22ULL 1.8V/3.3V SD/eMMC PHY AG2
  • TSMC N3E SD/eMMC PHY North/South Poly Orientation
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- TSMC N3E SD/eMMC PHY North/South Poly Orientation
  • TSMC N3P SD/eMMC PHY North/South Poly Orientation
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- TSMC N3P SD/eMMC PHY North/South Poly Orientation
  • xSPI + eMMC Combo PHY IP
    • This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support for two distinct memory protocols within the same IP.
    • By combining the PHY layers for both interfaces, the design simplifies system integration, reduces area and pin count, and enhances design flexibility for SoCs that require both boot and high-speed storage functionality.
    Block Diagram -- xSPI + eMMC Combo PHY IP
  • eMMC 5.1 HS400 PHY
    • The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification. It is backward compatible with eMMC4.51 and earlier versions of the specifications.
    • This allows the designers of the SoC to easily support the eMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 devices.
    Block Diagram -- eMMC 5.1 HS400 PHY
  • eMMC 5.1 Nex Bus Driver
    • eMMC 5.1 Nex Bus Driver is a production-ready software stack for eMMC 5.1 Host Controller IP that is used to connect eMMC devices.
    • The eMMC 5.1 stacks can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.
    Block Diagram -- eMMC 5.1 Nex Bus Driver
  • eMMC 5.1 Device I/O Pad
    • The eMMC 5.1 Device I/O is verified to be fully compliant I/O interface for JEDEC eMMC 5.1 when rectified and eMMC 5.0 JESD84-B50 specification. It is backward compliant with eMMC4.51 and earlier versions of the specifications.
    • This allows the designers of the SoC to easily support the EMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 hosts.
    Block Diagram -- eMMC 5.1 Device I/O Pad
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