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USB On-The-Go IP

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Compare 56 USB On-The-Go IP from 11 vendors (1 - 10)
  • USB 2.0 Host/Device Transceiver With On-The-Go (OTG)
    • Fully compliant with latest USB 2.0
    • Innovative technique to recover clock from 480 Mbps data.
    • High frequency PLL.
    • Advanced High-Speed Transmitter and Receiver.
    Block Diagram -- USB 2.0 Host/Device Transceiver With On-The-Go (OTG)
  • USB 2.0 On-The-Go IP Core, Compliance Certified
    • A ‘Dual-Role’ USB 2.0 On-The-Go IP Core that operates as both an USB 2.0 peripheral or as an USB 2.0 OTG host in a point-to-point communications with another USB device.
    • The USB OTG IP Core is fully USB 2.0 and USB 2.0 On-The-Go Supplement compliant.
    Block Diagram -- USB 2.0 On-The-Go IP Core, Compliance Certified
  • USB 2.0 PHY IP, Silicon Proven in UMC 40LP
    • Compliant with USB2.0 and USB1.1 specification
    • Compliant with UTMI Specification Version level 3.
    • Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
    • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
    Block Diagram -- USB 2.0 PHY IP, Silicon Proven in UMC 40LP
  • USB 3.0 PHY IP, Silicon Proven in UMC 40SP
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in UMC 40SP
  • USB 2.0 PHY IP, Silicon Proven in SMIC 40LL
    • Compliant with USB2.0 and USB1.1 specification
    • Compliant with UTMI Specification Version level 3.
    • Supports HS (480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
    • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
    Block Diagram -- USB 2.0 PHY IP, Silicon Proven in SMIC 40LL
  • USB 2.0 PHY IP, Silicon Proven in SMIC 55LL
    • Compliant with USB2.0 and USB1.1 specification
    • Compliant with UTMI Specification Version level 3.
    • Supports HS (480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
    • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
    Block Diagram -- USB 2.0 PHY IP, Silicon Proven in SMIC 55LL
  • USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
  • USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core
    • Support SW controlled host/device role switching.
    • Support Superspeed, Highspeed and Fullspeed
    • Support Control, Bulk, Interrupt and Isochronous Transfer Types
    • Support U1/U2/U3 power saving modes for USB 3.x port
    Block Diagram -- USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core
  • USB 3.1 SuperSpeed Dual-Role Device Controller (USB-IF Certified)
    • USB-IF Certified full-feature Dual Role Device Controller solution
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 3.1 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
    Block Diagram -- USB 3.1 SuperSpeed Dual-Role Device Controller (USB-IF Certified)
  • USB 3.1 SuperSpeed Device Controller (USB-IF Certified)
    • USB-IF Certified full-feature Device Controller solution
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 3.1 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
    Block Diagram -- USB 3.1 SuperSpeed Device Controller (USB-IF Certified)
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