PCI Express Controller IP
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PCI Express Controller IP
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184
PCI Express Controller IP
from 31 vendors
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PCIe Gen 7 Verification IP
- The PCIe Gen 7 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 7 interface of an IP or SoC.
- The PCIe Gen 7 VIP is fully compliant with latest PCI Express Gen 7 specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.
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PCIe Switch Verification IP
- Compliant with the PCIe 6,5,4,3 specification.
- Support Pipe Specification 6.1.1
- NVMe on top of Low Power, CXS, CPI, CXL, CXL Security, PCIe Gen6/5/4/3 management
- Supports Pipe Specification 6.1 with both Low Pin Count and Serdes Architecture.
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PCIe Gen 6 Verification IP
- Compliant with PCI Express Specifications 6.1 (64GT/s), 5.0 (32GT/s), 4.0 (16GT/s), 3.1 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
- Support for 64.0 GT/s Data Rate per lane with backwards compatible.
- Support for new PAM4 Signalling and Gray Coding.
- Support for both Flit Mode & Non-Flit Mode.
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PCIe Gen 5 Verification IP
- Support for 32.0 GT/s Data Rate per lane with backwards compatible.
- Optimizing the Link to skip equalization at lower Data Rates when supporting 32.0 GT/s(optional feature).
- Lower pin count in pipe interface when supporting 32.0 GT/s.
- Support for newly added phy serdes architecture in pipe specification 5.0 .
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PCIe Gen 2 Verification IP
- Compliant with PCI Express Specifications 2.0 (5GT/s) and 1.1 (2.5GT/s).
- Verification IP configurable as PCI express Root Complex and Device Endpoint.
- Configurable LinkWidth: x1, x2, x4, x8, x12, x16, x32.
- Configurable pipe width : 8,16,32,64
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PCIe Gen 6 controller IP
- Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32, 64 and 128-bit) specifications
- Supports SerDes Architecture PIPE 10b/20b/40b/80b width
- Supports original PIPE 8b/16b/32b/64b/128b width
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PCIe 6.0 / CXL 3.0 PHY & Controller
- Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
- These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications
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PCIe 5.0/4.0/3.0 PHY & Controller
- Innosilicon’s PCIe 5.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 5.0/4.0/3.0, and PIPE specifications
- These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, storage networks, automotive, and I/O connectivity applications
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FPGA Proven PCIe Gen6 Controller IP
- Supports up to x16 link width
- Support for Tx/Rx cut-through
- Supports 32 GT/s and 64 GT/s precoding
- Supports 14-bit tags for TLPs (Transaction Layer Packets)
- Supports buffering and credit management
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PCIe Switch for USB4
- Fully transparent design eliminates the need for Host configuration and management software
- Built-in support for PIPE-attached embedded endpoints (including 64-bit PIPE) for reduced BoM, latency, and power
- Seamless implementation on ASIC and FPGA with same RTL code base, up to x8 Gen4 per port on FPGA (or x16 Gen3)
- Lowest latency switching logic on the market (2 clock cycles)
