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AXI Bridge for PCIe IP Core

Overview

The AXI Bridge for PCIe IP core is the  IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.The AXI Bridge IP core translates the AXI4 memory read or writes to PCI-Express Transaction Layer Packets and translates PCIe memory read and write requests to AXI4 transactions.

All interfaces support fully parallel operation without any interferences. Interfaces that are not required can be turned off individually and do not occupy logic resources.

This IP core enables the developer to build complex PCI-Express endpoints with no specific PCI Express protocol know-how. The user only transmits or receives payload data and does not have to assemble valid PCI-Express TLP packets.

A powerful kernel mode device driver is shipped with the IP for Windows and Linux OS to ensure easy software integration of the core.

Key Features

  • Up to 4 S-AXI4 interfaces for bridging applications (incl peer to peer applications)
  • 6 AXI BARs with dynamic address translators
  • Non-blocking approach, an incomplete AXI packet does not block other AXI interfaces
  • Up to 8 AXI4 Masters to interface user registers
  • User transmits / receives only user data without PCIe protocol knowledge
  • Independent clocking and data width for each AXI interface
  • Built in completion sorting: S-AXI read requests are answered always in the requested order
  • High performance throughput: BVALID is asserted immediately after the end of the packet (WLAST)
  • Based on Xilinx / Intel / Lattice integrated PCI Sig compliant PCIe Block (HardIP)
  • Link speed Gen 1-4, link widths x1-x8
  • Available for most Xilinx, Intel and Lattice devices

Block Diagram

AXI Bridge for PCIe IP Core Block Diagram

Deliverables

  • Encrypted VHDL Source Code for easy Designflow integration
  • Comprehensive User Guide
  • Reference Design
  • Windows / Linux Driver Package (Option)
  • PCI-Express Testbench with High Speed simulation mode
  • Technical support

Technical Specifications

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AXI Bridge for PCIe IP Core
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