MIPI SLIMbus Synthesizable Transactor provides a smart way to verify the MIPI SLIMbus component of a SOC or a ASIC in Emulator or FPGA platform.The SmartDV's MIPI SLIMbus Synthesizable Transactor is fully compliant with standard MIPI SLIMbus 1.01.01/2.0 Specification and provides the following features.
MIPI SLIMBUS Synthesizable Transactor
Overview
Key Features
- Supports 1.01.01/2.0 MIPI SLIMbus Specification
- Supports organized TDM frame structure which allows SLIMbus to carry Control and Data information
- Supports unidirectional CLK line
- Supports up to eight bi-directional DATA line
- Enumeration for device is supported
- Supports Arbitration mechanism to access the port
- Supports limited retransmission of Messages
- Supports Frame layer to interleave Control space and data space in a Sub frame
- Ports make use of Isochronous, Pushed, Pulled and Asynchronous Protocols
- Supports all Core Message types
- Supports user Defined protocol
- Supports Flow control mechanism
- Supports Collision Detection for Message channel as well as for Data channel
- MIPI SLIMbus Synthesizable Transactor comes with complete test suite to test every feature of MIPI SLIMbus specification
- Supports error injection and error detection
- Supports various Error Management mechanisms
- Error on Segments
- Framing error
- Parity error
- Messaging error
- Error on Synchronization
- CRC error
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- Synthesizable transactors
- Complete regression suite containing all the MIPI SLIMbus testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
Benefits
Block Diagram
