Interface IP Cores

Designed with a small footprint, ultra-low latency, and low power consumption, the 112G SerDes maximizes bidirectional memory access efficiency, reduces software complexity, and helps chip developers leverage existing Ethernet infrastructure to significantly lower Total Cost of Ownership (TCO).
Featuring IEEE 802.3-compliant Forward Error Correction (FEC), 35dB ultra-high channel loss compensation, and adaptive high-speed equalization technologies (CTLE, FFE), it provides full-cycle link protection—from error correction to pre-warning—enabling highly compatible, stable, and efficient chip-to-chip connectivity solutions.

The ISO/IEC 7816 Verification IP offers a streamlined and efficient solution for verifying System-on-Chip (SoC) and IP designs that incorporate contactless communication.
The ISO/IEC 7816 VIP is compliant with ISO/IEC 7816 Specifications. This VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.

This VIP provides a comprehensive environment for verifying devices acting as either a Proximity Coupling Device (PCD) or a Proximity Integrated Circuit Card (PICC).
Fully compliant with the complete ISO/IEC 14443 standard (Parts 1-4), our VIP is a lightweight, plug-and-play solution designed to ensure rigorous verification, minimize design cycle time, and accelerate your time-to-market.

Fully compliant with Rev. 3.3.1 of the SMBus Specification.
Support PEC (Packet error Checking) for communication robustness.
Support for all Bus protocols with and without PEC.
Support for SMBus ARP (Address Resolution Protocol) for dynamically assigning a unique address to each slave device.
Support for Clock Synchronization & Arbitration for Multi Master.

Fully compliant with Rev. 6 of the I2C-Bus Specification and backward compatible upto 2.1 version
Full I2C Master and Slave functionality
- Master Transmitter/Master Receiver
- Slave Transmitter/Slave Receiver
Master Transmitter/Master Receiver
Slave Transmitter/Slave Receiver

The LPC Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC.
The LPC VIP is fully compliant with LPC Specification version 1.1
The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time.

Compliant with version 1.1 LPC Interface Specifications and eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
Converts eSPI Peripheral Channel Transactions into LPC Memory write or read instructions
Supports full LPC host capability
Supports SOC Slave