IP Catalog > Interface IP Cores

Interface IP Cores

Interface IP cores are used to achieve communication between chips and external devices or other chips. Common interface standards include USB, PCIe, SATA, I2C, SPI, Ethernet, etc.

Explore our vast directory of Interface IP cores below.

All offers in Interface IP Cores
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (3,393)
Compare 3,393 Interface IP Cores from 175 vendors (1 - 10)
  • MIPI CSI2 Receiver
    • Provides Compatible MIPI D-Phy v1.1 physical layer using FPGA LVDS/LVCMOS IO and passive network
    • Supports CSI-2 protocol for unidirectional data transfer
    • Compatible with D-PHY Configured for 1 clock and 4 data lanes
    • Intended for per-lane clocks rates up to 1 Gbps, depending on device speed grade
    Block Diagram -- MIPI CSI2 Receiver
  • MIPI CSI2 Transceiver
    • Provides Compatible MIPI D-Phy v1.1 physical layer using FPGA LVDS/LVCMOS IO and passive network
    • Supports CSI-2 protocol for unidirectional data transfer
    • Compatible with D-PHY Configured for 1 clock and 1 data lane
    • Intended for per-lane clocks rates up to 1 Gbps, depending on device speed grade
    Block Diagram -- MIPI CSI2 Transceiver
  • eUSB2V1.2 Controller + PHY IP
    • eUSB2 can support USB high-speed, full-speed, and low-speed operation, as well as the USB 2.0 L1/L2 link power management requirements. In addition, eUSB2 requires no change to the existing USB 2.0 software programming model.
    • eUSB2 also uses the same two data line configurations, eD+ and eD- as USB2 D+ and D-. Vbus and power delivery are not impacted by eUSB2.
    Block Diagram -- eUSB2V1.2 Controller + PHY IP
  • eUSB2V2.0 Controller + PHY IP
    • While traditional eUSB2 meets basic connectivity needs at 480 Mbps, modern SoCs and peripherals demand significantly higher throughput.
    • eUSB2-V2.0 bridges this gap by delivering up to 10× performance improvement, along with better power efficiency and EMI control — without changing the fundamental USB 2.0 software ecosystem.
    Block Diagram -- eUSB2V2.0 Controller + PHY IP
  • UALink Controller
    • The UALink Controller, part of Cadence’s verified UALink IP subsystem, delivers ultra-low latency and high-bandwidth interconnects that enable seamless scale-up connectivity between AI accelerators. I
    • t supports memory semantics for read, write, and atomic operations, ensuring fast, coherent data handling across workloads. UALink IP provides a scalable, future-ready solution for next-generation AI infrastructure.
    Block Diagram -- UALink Controller
  • UALink IP Solution
    • Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
    • Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
    • Enables maximum throughput with up to 200Gbps per lane
    • Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU
    Block Diagram -- UALink IP Solution
  • OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
    • The CT25210 Topology Discovery (TD) IP coordinates all operations required to perform 10BASE-T1S topology discovery measurements. It integrates several functional blocks, each responsible for a specific phase of configuration, training, measurement, and signal handling within the discovery process.
    • At the top level, the TD Manager supervises the measurement flow and configuration setup. Within this block, the TD Mode Manager manages the receive-only operating mode and distributes the necessary clock signals to other TD modules.
    Block Diagram -- OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
  • 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Configurable low latency parallel data interface for optimal system performance
    Block Diagram -- 32Gbps SerDes IP in TSMC 12nm FFC
×
Semiconductor IP