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Interface IP Cores

Interface IP cores are used to achieve communication between chips and external devices or other chips. Common interface standards include USB, PCIe, SATA, I2C, SPI, Ethernet, etc.

Explore our vast directory of Interface IP cores below.

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Search (3,381)
Compare 3,381 Interface IP Cores from 175 vendors (1 - 10)
  • DSC Encoder
    • Compliant with VESA DSC 1.2b, backward compatible with DSC 1.1
    • Supports all mandatory and optional coding schemes:
    • Modified Median-Adaptive Prediction (MMAP)
    • Midpoint Prediction (MPP)
    Block Diagram -- DSC Encoder
  • DSC Decoder
    • Compliant with VESA DSC 1.2b, backward compatible with DSC 1.1
    • Supports all mandatory and optional coding schemes:
    • Modified Median-Adaptive Prediction (MMAP)
    • Midpoint Prediction (MPP)
    Block Diagram -- DSC Decoder
  • DP and eDP TX/RX PHY IP
    • eDP v1.5 compliant
    • Supports for 1.62Gbps to Max 8.1Gbps data rate
    • PSR, PSR2 supported for low power consumption ( FW_SLEEP, FW_STANDBY supported )
    • Supports for eDP v1.5 feature such as AUX-less Link Training
    Block Diagram -- DP and eDP TX/RX PHY IP
  • MIPI C/D-PHY Combo IP
    • Compliant to MIPI D-PHY v3.0, C-PHY v2.1 specification
    • Area efficient macro optimized for placement for dense SoC designs
    • Support Uni-(TX or RX) and Bi-directional(TX and RX) mode
    • Support emphasis architecture over lossy channel for TX
    • Support equalize architecture over lossy channel for RX
    Block Diagram -- MIPI C/D-PHY Combo IP
  • DSI-2 TX/RX Controller
    • DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards.
    • Designed for modern SoCs integrating display functionality, it supports high-speed and low-power modes, lane configurability, and robust link features—making it ideal for advanced embedded display applications.
    Block Diagram -- DSI-2 TX/RX Controller
  • MIPI CSI-2 RX Controller
    • Lane merging, virtual channel detection, and programmable data extraction
    • Error detection and correction, including packet-level and protocol decoding errors
    • Supports all pixel formats defined in the CSI-2 standard
    Block Diagram -- MIPI CSI-2 RX Controller
  • 20G MSS (Multi-standard SerDes) PHY
    • Developing under SF4X CMOS technology (2025.06.30 MTO)
    • Compliant to multiple standards, max datarate 20Gb/s
    • Channel Configuration for Data Lanes: 1, 2 or 4 Data Lanes
    • Reliable Ring OSC PLL based architecture for Low power consumption
    Block Diagram -- 20G MSS (Multi-standard SerDes) PHY
  • PCIe Gen4.0 PHY IP
    • Best-in-class Power / Performance / Area competitiveness
    • Compliant to PCIe 4.0 Base specification
    • Supports lane configurations according to the user’s demands
    • Supports data rates of 2.5GT/s, 5.0GT/s, 8.0GT/s and 16GT/s
    Block Diagram -- PCIe Gen4.0 PHY IP
  • PCIe Gen5/6 PHY IP
    • Best-in-class Power / Performance / Area competitiveness
    • Compliant to PCIe 5.0/6.x Base specification
    • Supports lane configurations according to the customer’s demands
    • Supports data rates of 2.5GT/s, 5.0GT/s, 8.0GT/s, 16GT/s, 32GT/s and 64GT/s (PAM4)
    Block Diagram -- PCIe Gen5/6 PHY IP
  • 100G SerDes PAM4 PHY
    • The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
    • It supports diverse applications including AI accelerators, data centers, 5G infrastructure, and automotive SoCs.
    Block Diagram -- 100G SerDes PAM4 PHY
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