Interconnect IP
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2,499
Interconnect IP
from 154 vendors
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PCIe 6.2 Switch
- 1 upstream port, up to 7 downstream ports
- Up to 128 lanes
- PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
- L1 and wake-up events forwarding
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Scalable data path
- Advanced PIPE modes and port bifurcation
- Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
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Ethernet Enterprise Switch/Router IP Core - Efficient and Massively Customizable
- Full wire-speed on all ports and all Ethernet frame sizes.
- Store and forward shared memory architecture.
- Support for jumbo packets up to 32739 bytes.
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USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- Complies with USB specifications Rev. 2.0 and 1.1
- Complies with UTMI+ specification Level 3, Rev. 1.0
- Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
- Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
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USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- Complies with USB specifications Rev. 2.0 and 1.1
- Complies with UTMI+ specification Level 3, Rev. 1.0
- Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
- Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- Layout for wirebond packaging
- Very wide CDR range -- operates with data rates from 0.25Gbps to 8.1Gbps
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125Mbps to 16Gbps Multi-protocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
