MIPI IP for UMC
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51
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MIPI M-PHY IP
- The MIPI M-PHY is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY.
- The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC).
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MIPI DPHY v1.2 TX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY v1.2 RX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY Tx 2 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY Rx 2 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY Tx 4 Lanes - UMC 22ULP 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY Rx 4 Lanes - UMC 22ULP 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI MPHY v3.1, 2Tx-2Rx Type-1, UMC 22ULL 1.8V, N/S orientation
- Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
- High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
- Burst mode CDR with short sync length (< 16SI)
- Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
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MIPI DPHY_RX v1.2, 2C4D, UMC 28HPC+, E/W orientation
- Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
- Supports MIPI DSI and CSI-2 protocols
- Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
- Supports LS data rate of 10Mbps and Ultra-low power modes
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MIPI DPHY_TX v1.2, 1C4D, UMC 28HPC+, E/W orientation
- Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
- Supports MIPI DSI and CSI-2 protocols
- Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
- Supports LS data rate of 10Mbps and Ultra-low power modes
