Clock Generator PLL IP for UMC
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Clock Generator PLL IP
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Clock Generator PLL IP
for UMC
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10MHz to 50MHz fractional-N PLL synthesizer
- UMC 22nm ULP technology
- 1.8V IO power supply
- Double 0.8/1.0V Core power supply
- Embedded low noise bias
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Ultra low power 32.768 kHz crystal oscillator
- UMC 55nm eFlash CMOS technology
- Input Voltage 1.2V
- Fixed 32.768kHz output frequency
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Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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Fractional-N PLL for Performance Computing in UMC40LP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.02 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
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High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
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High Performance Fractional-N RF Frequency Synthesizer PLL in UMC 40LP
- Fractional-N digital PLL architecture, using an LC-tank oscillator
- Ultra-low jitter and ultra-low phase noise
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4-GHz Jitter-optimized low-power digital PLL
- - Jitter below 10-ps
- - Super small: 90 x 90 microns!
- - Very low power: 15-mW
- - Broad frequency range: 4-GHz
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UMC L28HPCLVT 28nm Clock Generator PLL - 220MHz-1100MHz
- Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
- Delivers optimal jitter performance over all multiplication settings.
- Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
- Ideal for system clock generation, SerDes and video clock applications.