IP for TSMC

One input word per clock without any backpressure
Design can switch stream, algorithm, mode, key and/or direction every clock cycle
GCM: throughput is solely determined by the data width, data alignment and clock frequency
XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available

The ODT-ADS-12B2400M-7T is an ultra low power ADC designed for use in a 6/7nm CMOS process.
This 12-bit, 400MSPS ADC supports input signals up to 200MHz and features a differential full-scale range of 1.0Vpp and excellent static and dynamic performance.

The ODT-LDO-IC-60M-7T-112 is a low dropout (LDO), linear regulator for integration in a SoC.
The LDO uses advanced control techniques to achieve excellent transient response, excellent PSRR performance and low noise.
The LDO has an integrated pass transistor and is stable with an on-chip capacitor of up to 250pF

The ODT-PVT-ULP-001C-7T is an ultra-low power temperature, voltage and process monitor designed in a 7nm CMOS process.
This IP operates over the entire temperature range of -40°C to 150°C.
The temperature monitor achieves ±4C temperature accuracy without trim and ±1C temperature accuracy after a single room temperature trim.

The ODT-ADS-12B250M-7T is an ultra-low power ADC designed in a 7nm CMOS process.
This 12-bit, 250MSPS ADC supports input signals up to 100MHz and features a differential full-scale range of 0.8Vpp and excellent static and dynamic performance.

The ODT-ADS-12B9G-16 is an ultra-highperformance time-interleaved ADC designed in a 16nm CMOS process.
This 12-bit, 9GSPS ADC supports input signals up to 3.0 GHz and features a differential fullscale range of 0.8Vpp and excellent static and dynamic performance.

The ODT-PVT-INT-001C-7 is an ultra-low power Temperature, Voltage and Process Monitor designed in a 7nm CMOS process.
This IP operates over the entire temperature range of -40°C to 125°C.
The Temperature Monitor (TM) achieves ±4°C temperature accuracy without trim and ±1°C temperature accuracy after a single room temperature trim.

Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7