MACsec Engine IP for TSMC

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Compare 6 MACsec Engine IP for TSMC from 2 vendors (1 - 6)
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  • 16nm
  • 100G / 200G / 400G / 800G / 1.6T MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially very high-speed Ethernet used in cloud, data center, and backhaul networks.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
    Block Diagram -- 100G / 200G / 400G / 800G / 1.6T MACsec
  • 10M MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially very low-speed Ethernet used in automotive, industrial, and consumer applications.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and is optimized for the smallest area size.
    Block Diagram -- 10M MACsec
  • 1G/2.5G/5G/10G/25G/50G MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially high-speed Ethernet used in automotive, industrial, cloud, data center, and wireless infrastructure.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
    Block Diagram -- 1G/2.5G/5G/10G/25G/50G MACsec
  • Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
    • One input word per clock without any backpressure
    • Design can switch stream, algorithm, mode, key and/or direction every clock cycle
    • GCM: throughput is solely determined by the data width, data alignment and clock frequency
    • XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
    Block Diagram -- Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
  • 800G Multi-Channel MACsec Engine with TDM Interface
    • Complete and fully compliant MACsec Packet Engine with classifier and transformation engines for rates of 100 to 800 Gbps, up to 64 channels, ready for FlexE
    • All IEEE MACsec standards supported (including IEEE802.1AE-2018). Optional inclusion of Cisco extensions, IPsec ESP tunnel and transport mode with AES-GCM cipher
    • Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
    Block Diagram -- 800G Multi-Channel MACsec Engine with TDM Interface
  • 1G to 50G Single-Port MACsec Engine with TSN support
    • Complete and compliant MACsec Packet Engine for rates from 1GbE to 50GbE with TSN support (including IEEE803.2br).
    • All IEEE MACsec standards supported (incl. IEEE802.1AE-2018). Optional Cisco ClearTags.
    • Supplied with the Driver Development Kit to accelerate time to market. Rambus offers MACsec Toolkit for IEEE 802.1X key management
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