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DSP Core IP for TSMC

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Compare 5 DSP Core IP for TSMC from 3 vendors (1 - 5)
  • Ultra-low-power Processor based on RISC-V Architecture
    • The icyflex-V processor is a new ultra-low-power core based on the RISC-V 32-bit ISA, compatible with off-the-shelf open-source and/or proprietary programming tools.
    • This new development represents a cost effective yet performing alternative to proprietary cores for next-generation ultra-low-power system-on-chip developments.
    • The core was optimized for performance, code density and power consumption and delivers up to 3.2 CoreMark/MHz while consuming as low as 14 uA/MHz in TSMC 55 nm low-power process.
    Block Diagram -- Ultra-low-power Processor based on RISC-V Architecture
  • Audio and control DSP
    • Quad 16x16 MACs
    • Dual 32x32 MACs
    • 4-way VLIW
    Block Diagram -- Audio and control DSP
  • Baseband processor
    • The Ceva-BX2 baseband processor IP handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming.
    • It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size.
    • Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators.
    Block Diagram -- Baseband processor
  • 24-bit General-purpose Fixed-point DSP Core, ADSP-218X Fully Compatible plus Enhancements
    • ADSP-218X Fully Compatible Architecture
    • 24/16-Bit Dual Mode
    • Other Enhancement
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Semiconductor IP