24-bit General-purpose Fixed-point DSP Core, ADSP-218X Fully Compatible plus Enhancements

Overview

Key Features

• ADSP-218X Fully Compatible Architecture
  • Fully Compatible Instructions (execution and timing).
  • Fully Compatible Interrupt Timing.
  • On-Core 16Kx24 PM and 16Kx24/16 DM.
  • YES, PM can store both code and data just like ADSP-218X.
  • ALU, MAC, Shifter Functional Units.
  • Two Data Address Generation Units (DAG).
  • IDMA and BDMA ports.
  • Single Cycle Execution.
  • Zero Overhead Looping.
  • Two Serial Ports.
  • Programmable Timer.
  • General Purpose I/Os.
  • Interrupt and Power-Down.
• 24/16-Bit Dual Mode
  • 24-bit and 16-bit Mode Dynamic Switching in Single Cycle.
  • Utilizing Same ADSP-218X Compiler/Assembler and development environment.
  • 24-bit ALU producing 24/16-bit results.
  • 56±24x24 MAC producing 24/16-bit results.
  • 48-bit Shifter producing 24/16-bit results.
  • 24-bit Arithmetic Registers.
  • 24-bit Internal Busses.
  • 24-bit Data Bus for PM and DM.
  • 24-bit External Bus.
  • 24-bit IDMA Port.
• Other Enhancement
  • Separate BDMA Port and IO Space.
  • Synchronous Dual-Access (within one cycle) design for both PM and DM.
  • One extra set of I, M, L Address Generator registers for more efficient Context Switching.
  • Powerful Min, Max Instructions.
  • Hooks for larger Register File.
  • Hooks for Instruction Set Extension.
  • Easily Configurable PM and DM sizes.
  • Expanded I/Os for easy embedding in SoC designs.
  • Flexible Expandable 24-bit DM (any words anywhere in the DM can be 24-bit wide)
  • Dynamic Frequency Change.
  • 3 Design Patents.

Benefits

• FULLY compatible to ADSP-218X
  • All standard ADSP-218X application codes run on it.
• FULLY synchronous and synthesizable design
  • ASIC as well as FPGA implementations are straight-forward and proven.
• Optimized for easy embedding in SOC designs
  • All I/Os are expanded (not multiplexed).
  • PM and DM sized are easily configured (changed) and optimized for target applications.
• Enhanced for more efficient coding and lower power operations
  • For the same application, WSP2416 code is expected to be smaller than the ADSP-218X code.
• Most optimized Mult/MAC design
  • Small, fast, and all Mult/MAC instructions complete in one cycle.
• High-Speed non-pipelined design
  • Purely scalar design (1MHz = 1MIPS).
  • All instructions complete in one clock cycle with NO exceptions.
  • Very small gate count.
  • 100+ MHz easily achieved in 0.25µm.

Deliverables

• Synthesizable Verilog source code
• Synthesis scripts
• Test Bench
• Test suites
• Documentation

Technical Specifications