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LVDS IP for TSMC

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Compare 81 LVDS IP for TSMC from 15 vendors (1 - 10)
  • HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm
    • A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.
    • This library is collection of analog only IO and Power/Ground pads that include ESD. The target applications are high performance analog interfaces including HDMI, RF, LVDS, basic analog and other applications.
    • The pads include a host of specialty features including fail safe, low capacitance, high ESD protection, and IEC robustness.
    Block Diagram -- HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm
  • 2.5V GPIO with 2Gbps LVDS RX TX and Analog Cell in GlobalFoundries 65nm LPe
    • A GlobalFoundries 65nm LPE Wirebond I/O library with 2.5V GPIO, 2Gbps LVDS TX RX and 2.5V Analog/RF cell with associated ESD.
    • A key attribute of this silicon-proven library include dual selectable drive strengths and independent input & output enable / disable.
    • The GPIO cell can be configured as input, output or open-drain with a Schmitt trigger input and selectable internal 60K ohm pull-up or pull-down resistor.
    Block Diagram -- 2.5V GPIO with 2Gbps LVDS RX TX and Analog Cell in GlobalFoundries 65nm LPe
  • 1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
    • A TSMC 28nm HPM/HPC/HPC+ Wirebond I/O Library with a switchable 1.8V/3.3V GPIO, 5V I2C ODIO, 1.8V & 3.3V Analog Cells, ESD and more.
    • A key attribute of this silicon-proven library is to detect and adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    • The GPIO can be configured as input, output, open-source, or open-drain with an optional 60kohm pull-up or pull-down resistor.
    Block Diagram -- 1.8V/3.3V Switchable GPIO with I2C, HDMI, LVDS, ESD & Analog in TSMC 28nm
  • Ultra-low leakage I/O Library in TSMC 22nm
    • A TSMC 22nm Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO, 1.8V analog cell and associated ESD.
    • This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD.
    • The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor.
    Block Diagram -- Ultra-low leakage I/O Library in TSMC 22nm
  • LVDS Transceiver
    • Meets or exceeds the TIA/EIA-644 LVDS standard.
    • Driver, Receiver, Bias, and Power cells included.
    • Greater than 400Mbs data rate.
    • 1.8V core voltage, 5V IO voltage.
    • Receive fault detection.
    • 0.3ns differential pulse skew.
    Block Diagram -- LVDS Transceiver
  • 1 Gbps Rail to Rail LVDS receiver
    • TSMC CMOS 0.065 um
    • 2.5 V analog power supply
    • 1.2 V digital power supply
    • 1.2 V CMOS input and output logic signals
    Block Diagram -- 1 Gbps Rail to Rail LVDS receiver
  • 2.4 Gbps LVDS transmitter
    • TSMC CMOS 0.065 um
    • 2.5 V analog power supply
    • 2.5 V CMOS input logic signals
    • 2.4 Gbps (DDR MODE) switching rates
    Block Diagram -- 2.4 Gbps LVDS transmitter
  • LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
    • The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
    • A phase-locked clock is transmitted in parallel with the data streams over a dedicated high-speed link.
    • The polarity of differential signals for each data lane can be controlled.
    Block Diagram -- LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
  • LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
    • The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data streams.
    • A phase-locked clock is transmitted in parallel with the data streams over a dedicated LVDS link.
    • The polarity of differential signals for each data lane can be controlled.
    Block Diagram -- LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
  • 500Mbps LVDS IP library
    • TSMC CMOS 180 nm
    • TIA/EIA-644 LVDS standards without hysteresis
    • Data transfer rate: up to 500Mbps (DDR MODE)
    Block Diagram -- 500Mbps LVDS IP library
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