Ultra-low leakage I/O Library in TSMC 22nm

Overview

A TSMC 22nm Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO, 1.8V analog cell and associated ESD.

This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. Cells for I/O and core power and ground with built-inESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The library includes pads for analog signals and a 6.5V one-time-programming voltage. The GPIO can do TX and RX up to 100MHz. The ODIO is I2C compliant. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.

Operating Conditions

Parameter Value
VDDIO 1.8V
Core VDD 0.8V
Temperature -40C to 125C
ESD 2kV HBM & 500V CDM

 Cell Size and Metal Stack

Cell Size Metal Stack
65um x 88um 1P7M_5x1Z

Cell Summary

Cell Type Feature
Supply/ESD 1.8V;0.8V; GND
GPIO 100MHz
ODIO I2C Compliant
VPP 6.5V tolerant
ANA 3.3V Analog I/O
Fill 1um, 5um and corner


 ESD Summary

  • GPIO complies with xSPI200
  • ODIO complies with I2C

Key Features

  • Typical leakage < 1nA
  • Worst-case leakage <80nA
  • 150MHz low-leakage general purpose I/O (GPIO)
  • High-speed 100MHz transmitter
  • Full-speed output enable
  • Independent power sequencing
  • Schmitt trigger receiver
  • 50K selectable pull-up or pull-down resistor
  • ESD: 2kV HBM, 500V CDM, 2kV IEC 61000-4-24

Block Diagram

Ultra-low leakage I/O Library in TSMC 22nm Block Diagram

Technical Specifications

TSMC
In Production: 22nm
Pre-Silicon: 22nm
Silicon Proven: 22nm
×
Semiconductor IP