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General-Purpose I/O (GPIO) IP for TSMC

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Compare 14 General-Purpose I/O (GPIO) IP for TSMC from 5 vendors (1 - 10)
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  • 16nm
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
  • 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
    • This library is a high-voltage GPIO I/O Macro in TSMC 16nm.
    • The high-voltage GPIO is a flip-chip compatible 1.8V to 3.3V GPIO design, compliant with multiple I/O standards.
    • It comes as a macro cell with a pair of I/Os in each cell, allowing differential I/O interface capabilities as well.
    Block Diagram -- 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
  • 1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm
    • This library is a production-quality, silicon-proven I/O Library in TSMC 16nm technology.
    • The High Performance GPIO is a flip-chip compatible, 1.2V to 1.8V GPIO design, compliant with multiple high-speed Single-Ended and Differential I/O standards.
    • The macro cell comes as a pair of I/Os that can be configured as a differential I/O or two independent single- ended I/Os.
    Block Diagram -- 1.2V/1.8V GPIO Compliant with multiple standards in TSMC 16nm
  • RGMII I/O offerings
    • RGMII
    • Physical Features
    Block Diagram -- RGMII I/O offerings
  • Secure Digital I/O offerings
    • Secure Digital
    • Physical Features
    Block Diagram -- Secure Digital I/O offerings
  • Block Diagram -- Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings
  • I/O Library
    • Dolphin Technology offers an extensive array of Interface IP, all of whichhasbeen optimized for ultra high performance across all processes supported.
    • Our I/O portfolio includes: Standard I/O (General Purpose I/O or GPIO), Specialty I/O (bus-specific I/O), NAND Flash I/O and DDRx & LPDDRx I/O.
  • TSMC N16FFC 1.2V/1.5V/1.8V/3.3v General Purpose IO with 3.3V Failsafe
    • Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and high-performance computing (HPC) applications
    • The IP is silicon-proven and available in several foundries and process technologies from 3nm to 22nm
    • Synopsys GPIO library is designed to support multiple voltages; it offers a complete set of support cells (supply, corner spacers, diode breakers, terminators) required to create complete I/O pad rings for system-on-chips (SoCs)
    • The library is compatible with flip-chip packaging
  • TSMC N16FFC 1.2V/1.5V/1.8V/3.3v General Purpose IO
    • Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and high-performance computing (HPC) applications
    • The IP is silicon-proven and available in several foundries and process technologies from 3nm to 22nm
    • Synopsys GPIO library is designed to support multiple voltages; it offers a complete set of support cells (supply, corner spacers, diode breakers, terminators) required to create complete I/O pad rings for system-on-chips (SoCs)
    • The library is compatible with flip-chip packaging
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