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I/O Library IP for TSMC

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Compare 362 I/O Library IP for TSMC from 20 vendors (1 - 10)
  • LVDS Transceiver
    • Meets or exceeds the TIA/EIA-644 LVDS standard.
    • Driver, Receiver, Bias, and Power cells included.
    • Greater than 400Mbs data rate.
    • 1.8V core voltage, 5V IO voltage.
    • Receive fault detection.
    • 0.3ns differential pulse skew.
    Block Diagram -- LVDS Transceiver
  • 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
    • 4MHz-35MHz Frequency range.
    • No external bias or limit resistors required.
    • Current optimization for best power at frequency.
    • Amplitude control loop.
    • The OSCI pad input can be used as a CMOS input for test.
    • Uses single 1.8V supply.
    • Enable/power down provision.
    Block Diagram -- 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
  • M31 eMMC/SDIO at TSMC 22ULP Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at TSMC 22ULP Process
  • M31 eMMC/SDIO at TSMC 22ULL Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at TSMC 22ULL Process
  • 1 Gbps Rail to Rail LVDS receiver
    • TSMC CMOS 0.065 um
    • 2.5 V analog power supply
    • 1.2 V digital power supply
    • 1.2 V CMOS input and output logic signals
    Block Diagram -- 1 Gbps Rail to Rail LVDS receiver
  • 2.4 Gbps LVDS transmitter
    • TSMC CMOS 0.065 um
    • 2.5 V analog power supply
    • 2.5 V CMOS input logic signals
    • 2.4 Gbps (DDR MODE) switching rates
    Block Diagram -- 2.4 Gbps LVDS transmitter
  • LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
    • The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
    • A phase-locked clock is transmitted in parallel with the data streams over a dedicated high-speed link.
    • The polarity of differential signals for each data lane can be controlled.
    Block Diagram -- LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
  • LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
    • The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into serial LVDS data streams.
    • A phase-locked clock is transmitted in parallel with the data streams over a dedicated LVDS link.
    • The polarity of differential signals for each data lane can be controlled.
    Block Diagram -- LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
  • 500Mbps LVDS IP library
    • TSMC CMOS 180 nm
    • TIA/EIA-644 LVDS standards without hysteresis
    • Data transfer rate: up to 500Mbps (DDR MODE)
    Block Diagram -- 500Mbps LVDS IP library
  • 1.2 Gbps LVDS transmitter/receiver
    • TSMC CMOS 180 nm
    • 3.3 V power supply
    • 1.2 Gbps (DDR MODE) switching rates (600 MHz)
    • Half-duplex or full-duplex operation mode
    Block Diagram -- 1.2 Gbps LVDS transmitter/receiver
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