I/O Library IP for TSMC

Compare 333 I/O Library IP for TSMC from 19 vendors (1 - 10)

Bi-Directional LVDS with LVCMOS
- Compliant with TIA/EIA-644 LVDS standard, also meets sub-LVDS
- Receiver compatible with HSCL levels for differential clock/data input
- LVDS transmitter and receiver have independent power control
- LVDS transmitter has adjustable output current level
3.3V general purpose I/O for 28nm CMOS
- Enable higher voltage operation, beyond the foundry IO levels
- Easily replace existing I/O cells
- Integrated scalable ESD protection
- Bias circuit can be shared with multiple I/Os
Library of LVDS IOs cells for TSMC 65LP
- TSMC 65 LP
- 2.5V/1.2V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
Library of LVDS IOs cells for TSMC 40LP
- TSMC 40 LP
- 2.5V/1.1V IO/Core transistors
- Fully compliant with TIA/EIA-644-A-2001
LVDS RX & TX IOs in multiple foundry technology
- LVDS TX
- LVDS RX
1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in 55nm
- 1.0V-3.3V | 3.3V IO operation
- Dual independent IO rails
- Output enable / disable (HiZ when disabled)
- Power-down control (HiZ upon VDD disable)
Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings
- I2C Open-drain
- Physical Features
Secure Digital I/O offerings
- Secure Digital
- Physical Features
RGMII I/O offerings
- RGMII
- Physical Features
A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
- GPIO:
- ANALOG
- OTP Programming Cell
- Physical Attributes