DSP & Math IP for TSMC

Compare 16 DSP & Math IP for TSMC from 10 vendors (1 - 10)

VHF/ UHF/L (DVB-H, DMB and ISDB-T) RF Front-end
- TSMC BiCMOS SiGe 180 nm technology
- Direct conversion receiver
- A few number of external components
- 0.18 um SiGe BiCMOS technology
6.5 to 23 MHz 3rd order low pass filter
- TSMC BiCMOS SiGe 180 nm
- Wide cut-off frequency adjustment range (6.5 MHz…23 MHz)
- Low pass filter cut-off frequency adjustment system
- Portable to other technologies (upon request)
150 MHz 5th order passive LPF
- TSMC 65 nm CRN65LP
- Differential inputs, outputs
- Fixed cut-off frequency 150 MHz
- High linearity
25/50/100 MHz 5th order passive LPF
- TSMC 65 nm CRN65LP
- Differential inputs, outputs
- Fixed cut-off frequency: 25 MHz, 50 MHz, 100 MHz
- High linearity
ITU G.704 E1 Framer/Deframer
- E1 framer/deframer compliant to G.704, G.706, G.732 and O.163 ITU recommendations.
- Supports CAS and CCS signalling standards.
- Supports CRC4 based framing standards.
- User configurable receive and transmit control.
ISDB-T1, Segment Tuner (470-860MHz UHF)
- High Performance
- Configurable 3/4 wire controller
- Self calibrating and programmable filter corner frequencies
- 8 Bit electronically tunable tracking filter
Fully Configurable Radix 2 FFT/IFFT Processor
- Radix-2 Fast Fourier Transform processor IP Core.
- Same IP core may be used to compute both FFT and IFFT transforms without any complexity overhead.
- Highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision.
- Bit true Matlab script model is provided to aid core fixed point precision configuration for any target application.
ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15
- Portable to all ASIC and FPGA technologies
Configurable SPDIF-AES3 Receiver
- The SPDIF-Rx-Pro (CWda14) is a digital audio receiver IP core supporting the SPDIF and AES3 and IEC60958 standards and also adds hardware support for the IEC61937 and SMPTE 337M standards for non-PCM (compressed) audio.
- This purely digital clock and data recovery method dispenses the classical analog PLL at the input reducing the receiver cost.
DVB-S2X-LDPC Decoder
- Irregular parity check matrix coding
- Layered Decoding
- Minimum sum algorithm
- Soft decision decoding
- ETSI EN 302 307-2 V1.1.1 compliant