IP Catalog > Foundries > TSMC > Analog IP > Clocking IP > PLL IP

PLL IP for TSMC

Welcome to the ultimate PLL IP for TSMC hub! Explore our vast directory of PLL IP for TSMC
All offers in PLL IP for TSMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (840)
Compare 840 PLL IP for TSMC from 26 vendors (1 - 10)
  • Low Power PLL for TSMC 40nm ULP
    • Wide range M, P, and N integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Input frequency range 1.4MHz – 32MHz.
    • 18pS RMS cycle to cycle jitter.
    • Lock-detect function.
    • Optional bypass function.
    Block Diagram -- Low Power PLL for TSMC 40nm ULP
  • General Purpose PLL for TSMC 152nm
    • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
    • 40MHz – 800MHz output frequency range.
    • Comparable frequency range 8MHz – 32MHz.
    • Optional prescaler.
    • 19pS RMS cycle to cycle jitter at 800MHz.
    • Lock-detect function.
    • Bypass function.
    • 20µS well defined fast startup behavior.
    Block Diagram -- General Purpose PLL for TSMC 152nm
  • PLL for TSMC 130nm LP
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 400MHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    • -40°C to 125°C temperature operation.
    • Small cell area: 0.022mm2 in 0.13µ CMOS.
    Block Diagram -- PLL for TSMC 130nm LP
  • Wide Range Programmable Integer PLL on TSMC CLN80GC
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Fully integrated inside customer-specified IO ring
    Block Diagram -- Wide Range Programmable Integer PLL on TSMC CLN80GC
  • Wide Range Programmable Integer PLL on TSMC CLN5A
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Small area footprint
    Block Diagram -- Wide Range Programmable Integer PLL on TSMC CLN5A
  • Wide Range Programmable Integer PLL on TSMC CLN55GP
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Fully integrated inside customer-specified IO ring
    Block Diagram -- Wide Range Programmable Integer PLL on TSMC CLN55GP
  • Wide Range Programmable Integer PLL on TSMC CLN16FFC
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Fully integrated inside customer-specified IO ring
    Block Diagram -- Wide Range Programmable Integer PLL on TSMC CLN16FFC
  • Low Power FracN/SSCG PLL on TSMC CLN6FF
    • Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Very fine precision: near 1 part per billion resolution
    • Fully integrated 32-bit datapath (8-bit integer plus 24-bit fractional)
    Block Diagram -- Low Power FracN/SSCG PLL on TSMC CLN6FF
  • FracN/SSCG PLL on TSMC CLN5
    • Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Very fine precision: near 1 part per billion resolution
    • Fully integrated 32-bit datapath (8-bit integer plus 24-bit fractional)
    Block Diagram -- FracN/SSCG PLL on TSMC CLN5
  • Core Powered Wide Range Programmable Integer PLL on TSMC CLN5A
    • Entirely core voltage powered, needs no analog supply voltage
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    Block Diagram -- Core Powered Wide Range Programmable Integer PLL on TSMC CLN5A
×
Semiconductor IP