DLL IP for TSMC
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405
DLL IP
for TSMC
from 5 vendors
(1
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10)
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800/1000 MHz DLL-based frequency multiplier
- TSMC 90 nm CMOS
- Low jitter
- Precisely aligns the clock distribution output with a reference clock
- Low current consumption
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30-200 MHz DLL-based frequency multiplier
- TSMC CMOS 55 nm
- 30 – 200 MHz output frequency
- 7.5 – 100 MHz reference frequency
- Multiplication factor 1, 2, 3 or 4
- Glitch-free mode switching
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Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
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High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
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4-GHz Jitter-optimized low-power digital PLL
- - Jitter below 10-ps
- - Super small: 90 x 90 microns!
- - Very low power: 15-mW
- - Broad frequency range: 4-GHz
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Minimum-area low-power clocking PLL (1st gen)
- - Super small: 80 x 80 microns!
- - Very low power: 12-mW
- - Broad frequency range: 2-GHz
- - Fast lock
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800Mb/s DDR DLL on TSMC CLN55LP
- Generates precise degrees of clock phase shifting for mobile or standard DDR applications
- Phase adjustments of non-continuous strobe clocks
- Compensates for external clock and data delays
- Programmable delay for precise and granular control of delay
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TSMC CLN3PLVT 3nm DDR DLL - 270MHz-1350MHz
- Designed for high-speed DDR style interface applications.
- Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
- Delays multiple periodic or aperiodic signals independent of voltage and temperature.
- Delivers optimal jitter performance over a wide frequency range.
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TSMC CLN3PLVT 3nm DDR DLL - 360MHz-1800MHz
- Designed for high-speed DDR style interface applications.
- Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
- Delays multiple periodic or aperiodic signals independent of voltage and temperature.
- Delivers optimal jitter performance over a wide frequency range.